Using contents of one array to index into another array

K

kb33

Guest
Hi,

I wanted to know whether it is possible to use the contents of one
array to index into another array in Verilog. For eg, in C language, it
would look somthing like...

int array1[10];
int array2[10];

/* Initialize each location in array1 to some value*/

array1[0] = 2;
array1[1] = 4;
array1[2] = 6;
..
..
..
..
..
..
..
array1[9] = 3;

/* Now, use the contents of array1 to index into array2*/

for (i = 0; i < 10; i++)
array2 [array1] = /* Do some computation, doesn't matter what..*/


Thanks,
Kanchan
 
kb33 wrote:
Hi,

I wanted to know whether it is possible to use the contents of one
array to index into another array in Verilog. For eg, in C language, it
would look somthing like...

int array1[10];
int array2[10];

/* Initialize each location in array1 to some value*/

array1[0] = 2;
array1[1] = 4;
array1[2] = 6;
.
.
.
.
.
.
.
array1[9] = 3;

/* Now, use the contents of array1 to index into array2*/

for (i = 0; i < 10; i++)
array2 [array1] = /* Do some computation, doesn't matter what..*/


Thanks,
Kanchan

You certainly can.
If you think of the outputs of memories like wires (think of a RAM chip
wired up with the address in and data out) you can wire those up to what
ever you want. In you case, the data of one memory drives the address
of another. Very valid.
 
HI,

Thanks for responding. The concept sounds doable, alright. However, my
question is more specific to the syntax - does Verilog allow double
indexing (what I illustrated in my previous email)? Also, I wish to run
through the FOR loop in 1 clock cycle and use non-blocking statements
for indexing into the second array (using the contents of the first
array).

Thanks,
Kanchan

John_H wrote:
kb33 wrote:
Hi,

I wanted to know whether it is possible to use the contents of one
array to index into another array in Verilog. For eg, in C language, it
would look somthing like...

int array1[10];
int array2[10];

/* Initialize each location in array1 to some value*/

array1[0] = 2;
array1[1] = 4;
array1[2] = 6;
.
.
.
.
.
.
.
array1[9] = 3;

/* Now, use the contents of array1 to index into array2*/

for (i = 0; i < 10; i++)
array2 [array1] = /* Do some computation, doesn't matter what..*/


Thanks,
Kanchan

You certainly can.
If you think of the outputs of memories like wires (think of a RAM chip
wired up with the address in and data out) you can wire those up to what
ever you want. In you case, the data of one memory drives the address
of another. Very valid.
 
I have no doubts that it will work fine.
But then I'm not a Verilog compiler guy, just a user.

Why not type it up and see if you get an error when you simulate it? It
seems to take significantly longer to talk about it than to do it.



kb33 wrote:
HI,

Thanks for responding. The concept sounds doable, alright. However, my
question is more specific to the syntax - does Verilog allow double
indexing (what I illustrated in my previous email)? Also, I wish to run
through the FOR loop in 1 clock cycle and use non-blocking statements
for indexing into the second array (using the contents of the first
array).

Thanks,
Kanchan
 

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