Using components in state machines

[Dave Smith]

Hello all -

I have a question regarding said topic in the subject line. I am
trying to use a previously created VHDL module (an 8-bit divider) in a
larger state machine architecture and I'm having some problems with
syntax. I have declared the module as a component as such:

component div8
port(
diva,divb : in std_logic_vector(7 downto 0);
div0 : out std_logic_vector(7 downto 0);
divq : out std_logic_vector(7 downto 0));
end component;

The state machine is based around a case statement that jumps to the
state that calls the divider whenever a control value is set to "%10".
Here are the lines of the state machine that deal with this:

variable divina,divinb,divoutq,divoutr : std_logic_vector(7 downto 0);
....
case ctrl is
....
--Divider unit
--Two 8-bit inputs, one 8-bit quotient and one 8-bit remainder
when "10" =>
divina := ina;
divinb := inb;
div8(divina,divinb,divoutr,divoutq);
outa <= divoutq;
outb <= divoutr;

As you can see, I'm calling the div8 module in the same manner as a
procedure (mapping the input/output variables through the parameter
list). I don't get any syntax errors when I do this, but the output is
VERY wrong also.

Is this even legal? How do you call a component from within a state
machine? Do I need to make the inputs signals instead of variables?

Thanks in advance for any insights, I can provide more code if
necessary!

 

[Mike Treseler]

Dave Smith wrote:

As you can see, I'm calling the div8 module in the same manner as a
procedure (mapping the input/output variables through the parameter
list). I don't get any syntax errors when I do this, but the output is
VERY wrong also.

Components are structural, not procedural.
In vhdl, procedural code can only be used inside a process.

See the procedure declaration and call for "ck_rising"
the the code example below. This will show you how
write procedural "components".

http://home.comcast.net/%7Emike_treseler/rise_count.vhd


-- Mike Treseler

 

[Dave Smith]

Mike Treseler wrote:

Components are structural, not procedural.
In vhdl, procedural code can only be used inside a process.

See the procedure declaration and call for "ck_rising"
the the code example below. This will show you how
write procedural "components".

http://home.comcast.net/%7Emike_treseler/rise_count.vhd


-- Mike Treseler

Interesting...so the only way to incorporate the two is to actually
take all the component code and implement it as a procedure? That
makes sense. Just out of curiosity, is there a way to convert the
structural element to a procedure type (kind of like type casting)?

The main reason I ask is the component architecture only contains a
single procedural process, so copying it over is simple but just
curious if it can be simplified even more...

Thanks again!

 

[Mike Treseler]

Dave Smith wrote:

Interesting...so the only way to incorporate the two is to actually
take all the component code and implement it as a procedure? That
makes sense. Just out of curiosity, is there a way to convert the
structural element to a procedure type (kind of like type casting)?

Sorry, it's one or the other.
Procedures and design entities
are fundamentally incompatible.
Fire and ice. Oil and water.
A house might be delivered to a construction
site as generic bricks and boards,
as prefabricated walls, or as a complete unit.

Procedures can be called by a process to construct
a single design entity of arbitrary complexity
using local variable declarations. The procedure
itself is just a template for part of a code
description. It has no ports to wire up.

Components/Instances can be used to duplicate and
wire together as many existing design entities as I want.
However, if I can't compose the brick I need
from others in the pile, I am stuck.

The main reason I ask is the component architecture only contains a
single procedural process, so copying it over is simple but just
curious if it can be simplified even more...

It is possible to combine two synchronous processes
as long as the variable declarations don't clash.
The drill is to put them both in my template
format and then shuffle together the procedures composing:
init_all_regs
update_process_regs
update_output_ports

-- Mike Treseler

 

[Dave Smith]

Awesome. Thanks!

 

I have very frequently controlled components from a state machine
which, of course, is not the same as incorporating a component in a
state machine. For example, one can increment/decrement and load a
counter by asserting the appropriate counter control signal and, in the
case of loading, setting the counter data input signal to the desired
value (if it is not always the same value). If you do this you should
be sure to avoid latches by assigning values to all of the control
signals in all states even when the values don't change. You can also
monitor the counter terminal count from within the state machine if
needed.

Charles

 

[Ralf Hildebrandt]

Dave Smith wrote:

component div8
port(
diva,divb : in std_logic_vector(7 downto 0);
div0 : out std_logic_vector(7 downto 0);
divq : out std_logic_vector(7 downto 0));
end component;

This is a component - or let's say a "block box".

variable divina,divinb,divoutq,divoutr : std_logic_vector(7 downto 0);
...
case ctrl is
...
--Divider unit
--Two 8-bit inputs, one 8-bit quotient and one 8-bit remainder
when "10" =
divina := ina;
divinb := inb;
div8(divina,divinb,divoutr,divoutq);
outa <= divoutq;
outb <= divoutr;

What you write here is something like a function / procedure. Such stuff
is a "resuable algorithm or construction plan to build a block box".


If you have a "block box" (component) in your design, you have to
connect some wires to it. If you want to connect different wires to it,
depending on something like a state you need multiplexers for the wires.

div8_instance : div8
port map(
diva=>wire_to_diva,
divb=>wire_to_divb,
div0=>wire_from_div0,
divq=>wire_from_divq );

You may do whatever you want (and what is legal) with these wires.

----------------
|your_component|
| ----------- |
| |black box| |
| ----------- |
----------------


Ralf