Using CAN on Zynq

[Heinz-Jürgen Oertel]

Hello,
might not be a real FPGA question,
but I hope that some of you doing not only the hardware part
but also working with the Xilinx SDK.
I try to use the CAN controller on e ZedBoard under Linux.
I *think* that I have done the CAN_L and CAN_H routing correct
to the FMC connector. Now I read and write to the CAN controller registers.
It seems to be correct, if I look what I'm reading back.
BUT, nothing happens at the CAN lines at the FMC connector.
What am I missing?
Do I need special clock settings in some other register, not CAN.
Or What else has to be programmed in order to get the CAN working?

Best regards
Heinz

 

[Martin Thompson]

Heinz-Jürgen Oertel <hj.oertel@t-online.de> writes:

Hello,
might not be a real FPGA question,
but I hope that some of you doing not only the hardware part
but also working with the Xilinx SDK.
I try to use the CAN controller on e ZedBoard under Linux.
I *think* that I have done the CAN_L and CAN_H routing correct
to the FMC connector. Now I read and write to the CAN controller registers.
It seems to be correct, if I look what I'm reading back.
BUT, nothing happens at the CAN lines at the FMC connector.
What am I missing?
Do I need special clock settings in some other register, not CAN.
Or What else has to be programmed in order to get the CAN working?

AFAIK, the Zedboard has no CAN physical layer on - how did you turn your
CAN Tx and Rx into CAN_H and CAN_L?

The CAN checklist goes:

* Have you got all the same "type" of PHY (there are high-speed,
low-speed, single-wire etc. variants)

* If high-speed, is the bus using twisted pair wiring?

* Is the bus a sensible length ("sensible" depends on bit-rate, wire
quality, and sundry other issues, so start with a small bus on the
bench ~2m)

* Is the bus terminated correctly?

* Have you another node on the bus to acknowledge the transmissions?

* Are all the nodes running with the same bit width and sampling point?

* Is the bus noise-free?

Do you have any CAN analysis tools (Canalyzer for example, or a
scope/logic analyser that understands the protocol)?

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[Heinz-Jürgen Oertel]

Martin Thompson wrote:

Heinz-Jürgen Oertel <hj.oertel@t-online.de> writes:

Hello,
might not be a real FPGA question,
but I hope that some of you doing not only the hardware part
but also working with the Xilinx SDK.
I try to use the CAN controller on e ZedBoard under Linux.
I *think* that I have done the CAN_L and CAN_H routing correct
to the FMC connector. Now I read and write to the CAN controller
registers. It seems to be correct, if I look what I'm reading back.
BUT, nothing happens at the CAN lines at the FMC connector.
What am I missing?
Do I need special clock settings in some other register, not CAN.
Or What else has to be programmed in order to get the CAN working?

AFAIK, the Zedboard has no CAN physical layer on - how did you turn your
CAN Tx and Rx into CAN_H and CAN_L?

The CAN checklist goes:

* Have you got all the same "type" of PHY (there are high-speed,
low-speed, single-wire etc. variants)

* If high-speed, is the bus using twisted pair wiring?

* Is the bus a sensible length ("sensible" depends on bit-rate, wire
quality, and sundry other issues, so start with a small bus on the
bench ~2m)

* Is the bus terminated correctly?

* Have you another node on the bus to acknowledge the transmissions?

* Are all the nodes running with the same bit width and sampling point?

* Is the bus noise-free?

Do you have any CAN analysis tools (Canalyzer for example, or a
scope/logic analyser that understands the protocol)?

Cheers,
Martin

Sorry I didn't check the forum for a long time.
In the mean time I solved all the problems.
can4linux is working now on the ZedBoard.
The CAN transceivers are on an FMC board, called ISM
http://www.em.avnet.com/en-us/design/drc/Pages/ISM-Networking-FMC-
Module.aspx

Regards
Heinz