S
Socrates
Guest
Hello,
I am trying to run SD-SDI interface on Cyclone II using Altera SDI
core. Since Cyclone II has no transceivers - soft-transceivers are
used, so I use PLL to generate 135MHz, 337.5MHz, 337.5MHz+90deg clocks
from 27MHz oscillator. The core is provided with these clocks, but
when I connect the SDI signal to SDI input, only RXCLK, which is
135MHz, and RX_DATA_VALID, which is about RXCLK/5, are provided on
output pins. I am sure I feed the real and correct SDI signal, but no
other outputs are working. Its strange that RX_DATA_VALID comes up,
even RX_DATA is always 0. Did I miss something? I don't know how to
debug core when all clocks are OK, input seems like OK, but nothing
goes out.
P.S. RX_RST and EN_SYNC_SWITCH are always tied to 0.
Thank You.
I am trying to run SD-SDI interface on Cyclone II using Altera SDI
core. Since Cyclone II has no transceivers - soft-transceivers are
used, so I use PLL to generate 135MHz, 337.5MHz, 337.5MHz+90deg clocks
from 27MHz oscillator. The core is provided with these clocks, but
when I connect the SDI signal to SDI input, only RXCLK, which is
135MHz, and RX_DATA_VALID, which is about RXCLK/5, are provided on
output pins. I am sure I feed the real and correct SDI signal, but no
other outputs are working. Its strange that RX_DATA_VALID comes up,
even RX_DATA is always 0. Did I miss something? I don't know how to
debug core when all clocks are OK, input seems like OK, but nothing
goes out.
P.S. RX_RST and EN_SYNC_SWITCH are always tied to 0.
Thank You.