Using aggregates for assignments

[Gary Thorpe]

Hi,

I am having a problem using aggregates to assign signal values. My code is:

(in entity port declaration)
SELECTED: out std_ulogic_vector(7 downto 0);
UDQM, LDQM: out std_ulogic

(in architecture of entity)
variable set_value: std_ulogic_vector(9 downto 0);

(in body of architecture)
--(SELECTED, UDQM, LDQM) <= set_value; -- this gives trouble
-- these are fine
SELECTED <= set_value(9 downto 2);
UDQM <= set_value(1);
LDQM <= set_value(0);

Is there a way to assign the signals as a group or is it just not valid VHDL code
(I can do the equivalent in Verilog by doing {SELECT, UDQM, LDQM} = set_value)?

The errors I get when I try to use the aggregate are:

(SELECTED, UDQM, LDQM) <= set_value;
^
Warning: vhdlan,734 file.vhd(62):
Discrete range is not consistent with corresponding index subtype (too few
elements).
(SELECTED, UDQM, LDQM) <= set_value;
^
**Error: vhdlan,720 file.vhd(62):
Name is not of the required type; STD_ULOGIC expected.

This is using the 'vhdlan' tool in Synopsys.

 

Gary Thorpe <gthorpe@ee.ryerson.ca> writes:

I am having a problem using aggregates to assign signal values. My code is:
...
The errors I get when I try to use the aggregate are:

(SELECTED, UDQM, LDQM) <= set_value;

The VHDL type system is getting in your way; try this:

(SELECTED(7), SELECTED(6), SELECTED(5), SELECTED(4),
SELECTED(3), SELECTED(2), SELECTED(1), SELECTED(0),
UDQM, LDQM) <= set_value;

Personally, I would use your other choice:

SELECTED <= set_value(9 downto 2);
UDQM <= set_value(1);
LDQM <= set_value(0);

--
Brian Ogilvie
brian dot ogilvie at mathworks dot com

 

[Mike Treseler]

Gary Thorpe <gthorpe@ee.ryerson.ca> wrote in message news:<caku20$g86$1@news.ryerson.ca>...

I am having a problem using aggregates to assign signal values. My code is:

(in body of architecture)
--(SELECTED, UDQM, LDQM) <= set_value; -- this gives trouble

http://groups.google.com/groups?q=vhdl+aggregate+hetzer

-- Mike Treseler

 

[Gary Thorpe]

bko-no-spam-please@ieee.org wrote:

Gary Thorpe <gthorpe@ee.ryerson.ca> writes:

I am having a problem using aggregates to assign signal values. My code is:
...
The errors I get when I try to use the aggregate are:

(SELECTED, UDQM, LDQM) <= set_value;

The VHDL type system is getting in your way; try this:

(SELECTED(7), SELECTED(6), SELECTED(5), SELECTED(4),
SELECTED(3), SELECTED(2), SELECTED(1), SELECTED(0),
UDQM, LDQM) <= set_value;

So aggregates must be composed of items with the same type?

Personally, I would use your other choice:

SELECTED <= set_value(9 downto 2);
UDQM <= set_value(1);
LDQM <= set_value(0);

I am also having trouble with this:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

port(
CS, RAS, CAS, WE: out std_logic;
..
..
..
(CS, RAS, CAS, WE) <= to_stdlogicvector("0010");
..
..
..
(CS, RAS, CAS, WE) <= "0001";

I try two different ways but both fail:

to_stdlogicvector("0010");
^
**Error: vhdlan,501 file.vhd(302):
Expression is ambiguous.
(CS, RAS, CAS, WE) <= "0001";
^
**Error: vhdlan,1021 file.vhd(315):
Can not determine type of right and left hand sides.

What am I doing wrong in this case? I would like to assign values to a group of
signals because together they define a logical operation (the four signals
define an SDRAM command for example). How do I do this properly?

--
Brian Ogilvie
brian dot ogilvie at mathworks dot com

Thanks for the quick reply.

 

Gary Thorpe <gthorpe@ee.ryerson.ca> writes:

So aggregates must be composed of items with the same type?

Or you have to use declarations or type qualifications which reduce the
attractiveness of left-hand side aggregates.

(CS, RAS, CAS, WE) <= to_stdlogicvector("0010");

Try this:

(CS, RAS, CAS, WE) <= to_stdlogicvector("0010")(3 DOWNTO 0);
or
(CS, RAS, CAS, WE) <= unsigned'("0010");

For this one, I would likely use:

CS <= '0'; RAS <= '0'; CAS <= '1'; WE <= '0';

which is pretty compact and easily understood.


--
Brian Ogilvie
brian dot ogilvie at mathworks dot com