Using a vector as an index

M

M. Hamed

Guest
Why is the Xilinx tool complaining about this (VHDL):

timer_done <= timer(data_len);

Where data_len is a 4 bit std_logic_vector, and timer is a 16 bit
std_logic_vector.

I want the tool to automatically infer a MUX with data_len as the
selector and timer as the input.

I can use a CASE statement but that is a lot of coding. I think
Verilog can happily accept that.

Thanks.
 
On May 22, 3:40 pm, "M. Hamed" <mhs...@gmail.com> wrote:
Why is the Xilinx tool complaining about this (VHDL):

timer_done <= timer(data_len);

Where data_len is a 4 bit std_logic_vector, and timer is a 16 bit
std_logic_vector.

I want the tool to automatically infer a MUX with data_len as the
selector and timer as the input.

I can use a CASE statement but that is a lot of coding. I think
Verilog can happily accept that.

Thanks.
Try this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- snip

timer_done <= timer(to_integer(unsigned(data_len));

Dave
 
On Thu, 22 May 2008 12:40:53 -0700 (PDT), "M. Hamed" <mhs000@gmail.com>
wrote:

Why is the Xilinx tool complaining about this (VHDL):

timer_done <= timer(data_len);

Where data_len is a 4 bit std_logic_vector, and timer is a 16 bit
std_logic_vector.
Because a 4-bit SLV is a collection of 4 bits, not a number.

If data_len was the unsigned type from ieee.numeric_std, you could write

timer_done <= timer(to_integer(data_len));

If it HAS to be an SLV (but why???) then

timer_done <= timer(to_integer(unsigned(data_len)));
is a bit more work, but also correct.

It may seem pedantic, but if you consider systems where that 4-bit
vector can be silently interpreted by the system as one of (unsigned,
signed, sign+magnitude, 1's complement, none of the above) and you may
or may not want the same interpretation; e.g. did you mean to step that
counter by +/-1 or +1/+15? you might see the point.

I prefer to explicitly say what I want to happen; not only to reduce the
chance of something unexpected happening, but also to make it easier for
someone ot understand later on...

- Brian
 

Welcome to EDABoard.com

Sponsor

Back
Top