Using a Mosfet

P

Peter Howard

Guest
I'm still working on the Mosfet power switching design I was fussing about
a fortnight ago. I'm a bit hamstrung by the fact that I've used Mosfets
before in other peoples designs but have never had to actually think about
them. I can make a stab at bipolar transistor design but FETs are a closed
book to me.

I've selected my Mosfet, a BUZ72A which has the current and voltage rating I
want. The question is, how to turn it on. Flowers, chocolate, liquor and
soft music don't work.

The data sheet Max Ratings says the max Gate/source voltage is +/- 20V.

The electrical characteristics say that the gate threshold voltage is Min 2V
Typical 2.9V and Max 4V
The same section gives the static Drain/Source resistance (low, as I want
it) for Gate/Source at 10V and Drain current of 5A.

I'm intending to send the gate low with an NPN transistor (BC548) turned on
hard when I want the FET turned off.

Question, what is the optimum voltage to apply to the FET gate when I want
the FET turned on hard? 10V?

Furthermore. Phil Allison in his reply to my previous post suggested a 63V
Zener, drain to source, to protect the FET from inductive spikes. I've since
seen a suggestion (on a 'Net hobby page) that a 15V Zener connected gate to
source will protect the gate from spikes.
It occurs to me that when I have decided on the optimum gate voltage, I
should connect a zener of that voltage gate to source. Feed it with a
resistor from the 12V supply which is also the load resistor of the NPN
transistor. When NPN transistor is not conducting, the zener-controlled
voltage is applied to the FET gate. When NPN transistor is turned on hard,
the gate/collector/resistor point goes low. Certainly lower than the the 2V
Min threshold voltage of the FET. Obviously, I'll choose a load resistor for
the NPN transistor which limits the collector current to a safe value. The
attraction of this idea is that the zener will alsodetermine the voltage to
be applied to the gate as well as protect against spikes.

Question, is it a stupid idea? Has any real designer ever done it this way?

PH
 
"Phil Allison" <philallison@tpg.com.au> wrote in message
news:3qbutvFe2fj4U1@individual.net...
"Peter Howard"

Question, what is the optimum voltage to apply to the FET gate when I
want the FET turned on hard? 10V?

** Yep.


Question, is it a stupid idea?


** Nope.


Has any real designer ever done it this way?


** Probably lots.



........... Phil


Thanks for the succinct reply. I went ahead tonight and built up and tested
Click to expand...
my design as described. The FET passed the desired current of 1A for several
hours with no signs of distress. Measured 0.15V across drain/source so I
guess it's turned on hard. Trivial for the experienced but a big thrill for
me when something actually goes as planned.
PH
 
"Peter Howard" <bbrover109@bbbigpond.net.au> wrote in message
news:v9c0f.6186$U51.5818@news-server.bigpond.net.au...
"Phil Allison" <philallison@tpg.com.au> wrote in message
news:3qbutvFe2fj4U1@individual.net...

"Peter Howard"

Question, what is the optimum voltage to apply to the FET gate when I
want the FET turned on hard? 10V?

** Yep.


Question, is it a stupid idea?


** Nope.


Has any real designer ever done it this way?


** Probably lots.



........... Phil


Thanks for the succinct reply. I went ahead tonight and built up and
tested
my design as described. The FET passed the desired current of 1A for
several
hours with no signs of distress. Measured 0.15V across drain/source so I
guess it's turned on hard. Trivial for the experienced but a big thrill
for
me when something actually goes as planned.
PH


Oddly enough, the thrill never goes away...... :)
Click to expand...

Ken
 
I'll elaborate slightly on Phils succint reply.

Peter Howard wrote:
I'm still working on the Mosfet power switching design I was fussing about
a fortnight ago. I'm a bit hamstrung by the fact that I've used Mosfets
before in other peoples designs but have never had to actually think about
them. I can make a stab at bipolar transistor design but FETs are a closed
book to me.

I've selected my Mosfet, a BUZ72A which has the current and voltage rating I
want. The question is, how to turn it on. Flowers, chocolate, liquor and
soft music don't work.
Click to expand...
lol

The data sheet Max Ratings says the max Gate/source voltage is +/- 20V.
Click to expand...
if you exceed that, you'll blow a hole thru the very thin gate oxide
layer, and bugger it. Some FETs have built-in gate zeners, in which case
you'll fry them.

its worth noting that many low-Vth FETs have +/-12V Vg_max.

The electrical characteristics say that the gate threshold voltage is Min 2V
Typical 2.9V and Max 4V
Click to expand...
Vth varies with temeprature, and from device to device. Use more than
4V, and it will always turn on.

The same section gives the static Drain/Source resistance (low, as I want
it) for Gate/Source at 10V and Drain current of 5A.
Click to expand...
there is probably a curve of Rdson vs Vgate. Rdson drops significantly
around Vth, then continues to decrease with increasing Vth, but only
slowly. If I^2Rdson is an issue, use more Vgate to get lower Rdson.

Rdson *increases* with junction temperature. worst case this can lead to
thermal runaway.
If you have a lousy heatsink, the device can run wuite a bit hotter
than expected, if the load current is constant (eg if Rdson is << Rload)

I'm intending to send the gate low with an NPN transistor (BC548) turned on
hard when I want the FET turned off.
Click to expand...
as long as Vcesat is << 2V, it'll work fine.

Question, what is the optimum voltage to apply to the FET gate when I want
the FET turned on hard? 10V?
Click to expand...
define "hard." 20V will give lower Rdson than 10V, which is lower than
4V. look at the diodes inc. 2N7002 data sheet.

oops, the missus just gave me a hard time. more later....

Furthermore. Phil Allison in his reply to my previous post suggested a 63V
Zener, drain to source, to protect the FET from inductive spikes. I've since
seen a suggestion (on a 'Net hobby page) that a 15V Zener connected gate to
source will protect the gate from spikes.
It occurs to me that when I have decided on the optimum gate voltage, I
should connect a zener of that voltage gate to source. Feed it with a
resistor from the 12V supply which is also the load resistor of the NPN
transistor. When NPN transistor is not conducting, the zener-controlled
voltage is applied to the FET gate. When NPN transistor is turned on hard,
the gate/collector/resistor point goes low. Certainly lower than the the 2V
Min threshold voltage of the FET. Obviously, I'll choose a load resistor for
the NPN transistor which limits the collector current to a safe value. The
attraction of this idea is that the zener will alsodetermine the voltage to
be applied to the gate as well as protect against spikes.

Question, is it a stupid idea? Has any real designer ever done it this way?

PH
Click to expand...
Cheers
Terry
 
"The Real Andy" <will_get_back_to_you_on_This@> wrote in message
news:9pf4k11ds02jft6o40nkodtov1mq07evem@4ax.com...
On Tue, 4 Oct 2005 08:18:04 +1300, "Ken Taylor" <ken@home.nz> wrote:

snip

Thanks for the succinct reply. I went ahead tonight and built up and
tested
my design as described. The FET passed the desired current of 1A for
several
hours with no signs of distress. Measured 0.15V across drain/source so
I
guess it's turned on hard. Trivial for the experienced but a big thrill
for
me when something actually goes as planned.
PH


Oddly enough, the thrill never goes away...... :)

Ken


It does when you get paid fuck as designer all and only ever
recognised when things go wrong.
Click to expand...
Buy Dilbert books and use the knowledge against the dark side of management.

Ken
 
On Tue, 4 Oct 2005 08:18:04 +1300, "Ken Taylor" <ken@home.nz> wrote:

<snip>

Thanks for the succinct reply. I went ahead tonight and built up and
tested
my design as described. The FET passed the desired current of 1A for
several
hours with no signs of distress. Measured 0.15V across drain/source so I
guess it's turned on hard. Trivial for the experienced but a big thrill
for
me when something actually goes as planned.
PH


Oddly enough, the thrill never goes away...... :)

Ken
Click to expand...
It does when you get paid fuck as designer all and only ever
recognised when things go wrong.
 
Terry Given wrote:
I'll elaborate slightly on Phils succint reply.

Peter Howard wrote:

I'm still working on the Mosfet power switching design I was fussing
about a fortnight ago. I'm a bit hamstrung by the fact that I've used
Mosfets before in other peoples designs but have never had to actually
think about them. I can make a stab at bipolar transistor design but
FETs are a closed book to me.

I've selected my Mosfet, a BUZ72A which has the current and voltage
rating I want. The question is, how to turn it on. Flowers, chocolate,
liquor and soft music don't work.


lol


The data sheet Max Ratings says the max Gate/source voltage is +/- 20V.


if you exceed that, you'll blow a hole thru the very thin gate oxide
layer, and bugger it. Some FETs have built-in gate zeners, in which case
you'll fry them.

its worth noting that many low-Vth FETs have +/-12V Vg_max.


The electrical characteristics say that the gate threshold voltage is
Min 2V Typical 2.9V and Max 4V


Vth varies with temeprature, and from device to device. Use more than
4V, and it will always turn on.

The same section gives the static Drain/Source resistance (low, as I
want it) for Gate/Source at 10V and Drain current of 5A.


there is probably a curve of Rdson vs Vgate. Rdson drops significantly
around Vth, then continues to decrease with increasing Vth, but only
slowly. If I^2Rdson is an issue, use more Vgate to get lower Rdson.

Rdson *increases* with junction temperature. worst case this can lead to
thermal runaway.
If you have a lousy heatsink, the device can run wuite a bit hotter
than expected, if the load current is constant (eg if Rdson is << Rload)


I'm intending to send the gate low with an NPN transistor (BC548)
turned on hard when I want the FET turned off.


as long as Vcesat is << 2V, it'll work fine.


Question, what is the optimum voltage to apply to the FET gate when I
want the FET turned on hard? 10V?


define "hard." 20V will give lower Rdson than 10V, which is lower than
4V. look at the diodes inc. 2N7002 data sheet.

oops, the missus just gave me a hard time. more later....


Furthermore. Phil Allison in his reply to my previous post suggested a
63V Zener, drain to source, to protect the FET from inductive spikes.
Click to expand...
the 63V zener is often not needed. most FETs are spec'd for avalanche
energy (note: any zener above about 4V is actually an
avalanche-breakdown diode), and as long as the spike energy is less than
this, the FET will happily "zener" all by itself. the key phrase in a
datasheet is "unclamped inductive load". FETs were originally not very
good in this respect....

I've since seen a suggestion (on a 'Net hobby page) that a 15V Zener
connected gate to source will protect the gate from spikes.
Click to expand...
again, many FETs have these diodes built in. but yes. it doesnt even
have to be a zener - a diode to a +15V (or say +9V etc) supply, with a
decent cap (say 100nF) is often cheaper, and works just fine.

It occurs to me that when I have decided on the optimum gate voltage,
I should connect a zener of that voltage gate to source.
Click to expand...
look at the datasheet for a zener. often the voltage is pretty loose,
and moves with temperature. the higher Vz, the greater the tempco.

Anyway, this is actually unnecessary. if you have a 12V supply and
+/-20V Vg_max, then any zener from 13-18V will work fine (note I kept
the zener voltage *below* Vg_max and above Vcc, that way you can ignore
its tolerance)

Feed it with
a resistor from the 12V supply which is also the load resistor of the
NPN transistor. When NPN transistor is not conducting, the
zener-controlled voltage is applied to the FET gate. When NPN
transistor is turned on hard, the gate/collector/resistor point goes
low. Certainly lower than the the 2V Min threshold voltage of the FET.
Obviously, I'll choose a load resistor for the NPN transistor which
limits the collector current to a safe value. The attraction of this
idea is that the zener will also determine the voltage to be applied to
the gate as well as protect against spikes.

Question, is it a stupid idea? Has any real designer ever done it this
way?
Click to expand...
in general more Vg is better, as long as the FET doesn't break.

most designers pick the zener to clamp gate spikes rather than "control"
Vg. Check zener tolerance and voltage variation with zener current....

the disadvantage with this approach is that the NPN transistor Ic
constraint sets Rgate, and the gate time constant is then whatever it is
- Rgate*Cgs. slow turn ON, fast turn OFF. If switching at a low
frequency, then who cares - I once built 17,000 OEM UPS' (inside
terabyte RAID arrays) that had 47k pullups, no zener but otherwise your
circuit.


PH


Cheers
Terry
Click to expand...
 
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