using 2 If statements

Hey all,
I am using Verilog-a.. well my code is something like :

If(Vdata[1]==V(avss) & V(data[0] == V(avss)begin
if (V(in) <= -vmind)
state = 2 *V(vin);
end

Now is the first if statement evaluated and then if its satisfied the
second if statement will be evaluated? or are they both evaluated at
the same time?


Thanks
KARMEL

 

[Jason Zheng]

Karmel.Abdeljawad@gmail.com wrote:

Hey all,
I am using Verilog-a.. well my code is something like :

If(Vdata[1]==V(avss) & V(data[0] == V(avss)begin
if (V(in) <= -vmind)
state = 2 *V(vin);
end

Now is the first if statement evaluated and then if its satisfied the
second if statement will be evaluated? or are they both evaluated at
the same time?


Thanks
KARMEL

They are evaluated in sequence. In fact if the first condition in the

first if state is false, the second condition isn't evaluated either.

~jz