useless synthetized blocks

[Max]

I tried to implement a decoder in two differnet way:
--------------8<-------------------------
entity main is
Generic (w : integer := 12);
Port ( addr : in std_logic_vector(3 downto 0);
ce : in std_logic;
y : out std_logic_vector(w-1 downto 0));
end main;

architecture Behavioral of main is

begin

-- first way
process (addr, ce)
begin
y <= (others => '0');
if (addr < w and ce = '1') then
y(to_integer(unsigned(addr))) <= '1';
end if;
end process;

-- second way
--y <= (others => '0') when ce = '0' else
-- "000000000001" when addr = "0000" else
-- "000000000010" when addr = "0001" else
-- "000000000100" when addr = "0010" else
-- "000000001000" when addr = "0011" else
-- "000000010000" when addr = "0100" else
-- "000000100000" when addr = "0101" else
-- "000001000000" when addr = "0110" else
-- "000010000000" when addr = "0111" else
-- "000100000000" when addr = "1000" else
-- "001000000000" when addr = "1001" else
-- "010000000000" when addr = "1010" else
-- "100000000000" when addr = "1011" else
-- (others => '0');

end Behavioral;
--------------8<-------------------------

I prefer the firsr version since I don't need to rewrite the code if
generic 'w' changes.
After synthesis the device utilization is exacly the same, but looking
at rtl schematics (I use xilinx webpack ise) there is a differce:
in the first way is synthetized a comparator. This is correct but
useless since the other logic can provide its function.

there is another way to avoid the presence of comparator?

thanks

 

[Mike Treseler]

Max wrote:

I prefer the firsr version since I don't need to rewrite the code if
generic 'w' changes.

I agree.

After synthesis the device utilization is exacly the same,

That's all that matters.

but looking
at rtl schematics (I use xilinx webpack ise) there is a differce:
in the first way is synthetized a comparator. This is correct but
useless since the other logic can provide its function.

there is another way to avoid the presence of comparator?

The RTL schematic is a logical view,
not an optimized netlist.

The comparator is not a real logic block.

The technology schematic shows how
the actual logic blocks will be used.

-- Mike Treseler