V
vladimir
Guest
TBGenerator - generates test benches which was described by Verilob or
VHDL. Works with inout ports. Additional tools - convert time to
frequency and frequency to time, create component declaration.
Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk embedded
interpreter.
www.hightech-td.com
VHDL. Works with inout ports. Additional tools - convert time to
frequency and frequency to time, create component declaration.
Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk embedded
interpreter.
www.hightech-td.com