use work.xxxx.all in ispLever 7.0 different than Quartus?

R

Richard Klingler

Guest
Evnin'

Somebody knwos why ispLever bails out with:

# Warning: [43092]: "t80_ip/T80.VHD", line 73: T80_Pack does not denote
a library or package.
# Error: [42512]: "t80_ip/T80.VHD", line 307: Use of undeclared
identifier 'T80_MCode'
# Error: [40000]: HDL analysis failed.


....whereas in Altera Quartus 7.1 it's fine?


thx in advance
rick
 
"Richard Klingler" <me@aol.com> wrote in message
news:O7adnfLNwvbCqCPbRVnyiwA@giganews.com...
Evnin'

Somebody knwos why ispLever bails out with:

# Warning: [43092]: "t80_ip/T80.VHD", line 73: T80_Pack does not denote a
library or package.
# Error: [42512]: "t80_ip/T80.VHD", line 307: Use of undeclared identifier
'T80_MCode'
# Error: [40000]: HDL analysis failed.


...whereas in Altera Quartus 7.1 it's fine?


thx in advance
rick
Click to expand...
Whatever file(s) that defines 'T80_Pack' and 'T80_MCode' is either...
- Not in the list-o-files in your ispLever project (but is in your Quartus
project)
- Is not listed in the ispLever project prior to the file 't80_ip/T80.vhd'.

KJ
 
KJ schrieb:
"Richard Klingler" <me@aol.com> wrote in message
news:O7adnfLNwvbCqCPbRVnyiwA@giganews.com...
Evnin'

Somebody knwos why ispLever bails out with:

# Warning: [43092]: "t80_ip/T80.VHD", line 73: T80_Pack does not denote a
library or package.
# Error: [42512]: "t80_ip/T80.VHD", line 307: Use of undeclared identifier
'T80_MCode'
# Error: [40000]: HDL analysis failed.


...whereas in Altera Quartus 7.1 it's fine?


thx in advance
rick

Whatever file(s) that defines 'T80_Pack' and 'T80_MCode' is either...
- Not in the list-o-files in your ispLever project (but is in your Quartus
project)
- Is not listed in the ispLever project prior to the file 't80_ip/T80.vhd'.

KJ
Click to expand...
No...it is listed on top as "package"...but it is a mixed verilog/vhdl
design so it messes up either ispLever or Precision RTL...

So when I choose the VHDL top file inside the Verilog/VHDL mixed design
and choose on the right pane to synthesize this with Precision then it
works...

It just throws this error when I compile the whole design...

Lattice's own version of Synplifo is no option as it does not allow
mixed Verilog/VHDL designs...


So seems that ispLever still doesn't support mixed designs as
it says...


cheers
rick
 
"Richard Klingler" <me@aol.com> wrote in message
news:bYednXTr3uPE9CLbRVnygQA@giganews.com...
KJ schrieb:
"Richard Klingler" <me@aol.com> wrote in message
news:O7adnfLNwvbCqCPbRVnyiwA@giganews.com...
Evnin'

Somebody knwos why ispLever bails out with:

# Warning: [43092]: "t80_ip/T80.VHD", line 73: T80_Pack does not denote
a library or package.
# Error: [42512]: "t80_ip/T80.VHD", line 307: Use of undeclared
identifier 'T80_MCode'
# Error: [40000]: HDL analysis failed.


...whereas in Altera Quartus 7.1 it's fine?


thx in advance
rick

Whatever file(s) that defines 'T80_Pack' and 'T80_MCode' is either...
- Not in the list-o-files in your ispLever project (but is in your
Quartus project)
- Is not listed in the ispLever project prior to the file
't80_ip/T80.vhd'.

KJ



No...it is listed on top as "package"...but it is a mixed verilog/vhdl
design so it messes up either ispLever or Precision RTL...

So when I choose the VHDL top file inside the Verilog/VHDL mixed design
and choose on the right pane to synthesize this with Precision then it
works...

It just throws this error when I compile the whole design...

Lattice's own version of Synplifo is no option as it does not allow
mixed Verilog/VHDL designs...


So seems that ispLever still doesn't support mixed designs as
it says...


cheers
rick

Then I guess you'll need to open a service request with Lattice.
Click to expand...

KJ
 
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