Use of Both Posedge Clk and Negedge Clock...

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[e liu]

ppo...@gmail.com 在 2005年5月27日 星期五下午5:20:48 [UTC+8] 的信中寫道：

using posedge and negedge clk , in fact, is equal to always @ ( clk or
negedge reset )

I am facing the same situation when writing a FSM, and I wonder if I can seperate the posedge and nededge always.
For example:
always@(posedge clk or posedge rst) case(current_state) case1: .... case2: ....... case3:.......
always@(nededge clk or posedge rst) case(current_state) case1: .... case3:........

 

[gnuarm.del...@gmail.com]

On Friday, June 23, 2023 at 10:19:59 PM UTC-4, e liu wrote:

ppo...@gmail.com 在 2005年5月27日 星期五下午5:20:48 [UTC+8] 的信中寫道：
using posedge and negedge clk , in fact, is equal to always @ ( clk or
negedge reset )
I am facing the same situation when writing a FSM, and I wonder if I can seperate the posedge and nededge always.
For example:
always@(posedge clk or posedge rst) case(current_state) case1: .... case2: ...... case3:.......
always@(nededge clk or posedge rst) case(current_state) case1: .... case3:.......

Stop thinking in terms of the code. Think in terms of what hardware you expect to have generated. Then describe the actions of that hardware, and the tools will follow your instructions. It\'s call a Hardware Description Language for a reason... \"HARDWARE DESCRIPTION\". So, describe the hardware you want built. If you don\'t know what that hardware is, how will the tools know???

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Rick C.

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