Use of Both Posedge Clk and Negedge Clock

[Chloe]

Hello everyone,

A couple of questions to all the Verilog experts from a Verilog newbie:

1. What are the implications of coding a flip-flop with both posedge of
clock and negedge of clock in the sensitivity list, ie

always @ (posedge clock or negedge clock or negedge reset)
begin
.....
end

2. How would the use of the above affect synthesis? Will a design be
synthesizable if it contains RTL with dual edge-triggered clocks?

Please help.

Thanks very much in advance.

-Chloe-

 

[Neo]

if your library supports dual edge FFs then its synthesizable else it
will throw an error. AFAIK there are no such libraries supported at
this time except in some cplds.

 

[Berty]

Since FF have generally speaking only one clock (unless you have
special libraries which are rarely the case) it will be more advisable
to use for example double the clock and than use only posedge (or only
negedge) of the clock.

Have fun.

 

[Chloe]

The problem is, I'm only using one clock, which frequency cannot be
doubled. The limitations of the design is such that I can only use one
clock, and this clock drives a counter at the same speed, ie the each
count is one clock period. This will still pass functionally, but I
worry about setup and hold violations later during synthesis.

I tried using two flip flops - one driving at posedge, and the other at
negedge of clk.

Any suggestions?

 

using posedge and negedge clk , in fact, is equal to always @ ( clk or
negedge reset )