USE clause for cell library

D

David C Hendry

Guest
Hello,

I have an architecture body generated by a synthesis tool that contains
component declarations referring to a standard cell library. If I modify
that architecture body to include prior to the architecture body itself):

library celllib;
use celllib.all;

then all compiles, elaborates and synthesises, so I assume that the cell
library format and permissions and so on are OK. If however I write a
configuration, and here's the code (the design is called "example1", the
testbench is "example1_tb" with architecture name "tb", and the synthesised
netlist has architecture name "netlist", the instance name for the
synthesised design is "dut"):

library celllib;

configuration example1_tb_cfg_net of example1_tb is

for tb
for dut : example1
use entity work.example1(netlist);
for netlist
use celllib.all;
end for;
end for;
end for;

end example1_tb_cfg_net;

then this code compiles (IUS 8.1), but at elaboration time the components
within the netlist are not bound. Any ideas?
 
Where I said "compiles, elaborates and synthesises" I did of course mean
"compiles, elaborates and simulates"! Sorry.
 
David C Hendry wrote:

then this code compiles (IUS 8.1), but at elaboration time the components
within the netlist are not bound. Any ideas?
Click to expand...
Configurations are too complicated
for such a simple problem.
Just compile one architecture or the other.
See Jonathan here:
http://groups.google.com/groups/search?q=vcom+just+gaindiv

-- Mike Treseler
 
Hello Mike,

Well I'd have to agree with that! I'm actually trying to come to grips with
all that configurations can do! My worry here is that in a real case the
netlist will be generated many times as synthesis is tuned, so I don't want
to have to edit the netlist each time to indicate the target library. Ah
well, just do as you suggest it seems.

David.
"Mike Treseler" <mtreseler@gmail.com> wrote in message
news:494134F7.9040208@gmail.com...
David C Hendry wrote:

then this code compiles (IUS 8.1), but at elaboration time the components
within the netlist are not bound. Any ideas?

Configurations are too complicated
for such a simple problem.
Just compile one architecture or the other.
See Jonathan here:
http://groups.google.com/groups/search?q=vcom+just+gaindiv

-- Mike Treseler
Click to expand...
 
There is no component configuration inside the block configuration
for the "netlist" architecture. That is just a USE clause, and is
not making visible anything that is actually being used (i.e., that
USE clause does nothing of consequence in the absence of actually
using something that the USE clause makes directly visible).

By the way, if the architecture itself contains the component declarations
used in the component instantiation statement(s) in that architecture,
and you're not doing any direct instantiations (which would leave those
component declarations unused), I presume that "use celllib.all" is above
the architecture declaration is simply making entities (and/or
configuration declarations) visible for those component instantiations
to use for binding to. Are there any configuration specifications in
the architecture, or are you doing default binding?



David C Hendry wrote:
Hello,

I have an architecture body generated by a synthesis tool that contains
component declarations referring to a standard cell library. If I modify
that architecture body to include prior to the architecture body itself):

library celllib;
use celllib.all;

then all compiles, elaborates and synthesises, so I assume that the cell
library format and permissions and so on are OK. If however I write a
configuration, and here's the code (the design is called "example1", the
testbench is "example1_tb" with architecture name "tb", and the synthesised
netlist has architecture name "netlist", the instance name for the
synthesised design is "dut"):

library celllib;

configuration example1_tb_cfg_net of example1_tb is

for tb
for dut : example1
use entity work.example1(netlist);
for netlist
use celllib.all;
end for;
end for;
end for;

end example1_tb_cfg_net;

then this code compiles (IUS 8.1), but at elaboration time the components
within the netlist are not bound. Any ideas?
Click to expand...
 
David C Hendry wrote:

Well I'd have to agree with that! I'm actually trying to come to grips with
all that configurations can do! My worry here is that in a real case the
netlist will be generated many times as synthesis is tuned, so I don't want
to have to edit the netlist each time to indicate the target library.
Click to expand...
It is disappointing that vhdl configurations do not
provide a *simple* way to cover gate vs rtl sims.
But even if it did, the solution would be incomplete.

Most verification schemes involve some sort
of makefile or script to handle simulation
options and dependencies anyway.
If this is your case, rtl/gate and library options
can be handled as any other.

If you are interested, google back into
the previous century of this group.
There are some amazing and mind-numbing
threads on vhdl configuration details.

-- Mike Treseler
 
Hi, Default bindings are used throughout. I've tried explicit bindings in
the configuration declaration, and these work as expected, but of course,
with a potentially changing netlist I'd have preferred to avoid that.

Kindest regards, David.

"James Unterburger" <jamesu@europa.com> wrote in message
news:ghrhlf$pou$1@aioe.org...
There is no component configuration inside the block configuration
for the "netlist" architecture. That is just a USE clause, and is
not making visible anything that is actually being used (i.e., that
USE clause does nothing of consequence in the absence of actually
using something that the USE clause makes directly visible).

By the way, if the architecture itself contains the component declarations
used in the component instantiation statement(s) in that architecture,
and you're not doing any direct instantiations (which would leave those
component declarations unused), I presume that "use celllib.all" is above
the architecture declaration is simply making entities (and/or
configuration declarations) visible for those component instantiations
to use for binding to. Are there any configuration specifications in
the architecture, or are you doing default binding?



David C Hendry wrote:
Hello,

I have an architecture body generated by a synthesis tool that contains
component declarations referring to a standard cell library. If I modify
that architecture body to include prior to the architecture body itself):

library celllib;
use celllib.all;

then all compiles, elaborates and synthesises, so I assume that the cell
library format and permissions and so on are OK. If however I write a
configuration, and here's the code (the design is called "example1", the
testbench is "example1_tb" with architecture name "tb", and the
synthesised netlist has architecture name "netlist", the instance name
for the synthesised design is "dut"):

library celllib;

configuration example1_tb_cfg_net of example1_tb is

for tb
for dut : example1
use entity work.example1(netlist);
for netlist
use celllib.all;
end for;
end for;
end for;

end example1_tb_cfg_net;

then this code compiles (IUS 8.1), but at elaboration time the components
within the netlist are not bound. Any ideas?
Click to expand...
 
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