Use BRam and DRam on FPGA's Xilinx

[Gordon Freeman]

Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only
use slices resources. But I want to use BRam or DRam resources on FPGA
(FPGA's Xilinx) to generate RAM or ROM. Can you help me?

 

[Andy]

The most common reason people get flops/gates when the wanted RAM is
that they are reading/writing more than one (single port) or two (dual
port) elements of the same array in the same clock cycle.

Review your code to ensure this is not happening.

Andy

On Apr 15, 9:27 pm, "Gordon Freeman" <gordonfreeman1...@gmail.com>
wrote:

Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only
use slices resources. But I want to use BRam or DRam resources on FPGA
(FPGA's Xilinx) to generate RAM or ROM. Can you help me?

 

[Andy Peters]

On Apr 15, 7:27 pm, "Gordon Freeman" <gordonfreeman1...@gmail.com>
wrote:

Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only
use slices resources. But I want to use BRam or DRam resources on FPGA
(FPGA's Xilinx) to generate RAM or ROM. Can you help me?

Depending on the FPGA family, you need to describe a synchronous read
in order to infer a BRAM.

-a

 

[Matthias Alles]

Hi!

Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding
techniques. This chapter describes detailed which HDL constructs will
result in the usage of which FPGA resource.

Matthias


Gordon Freeman schrieb:

Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only
use slices resources. But I want to use BRam or DRam resources on FPGA
(FPGA's Xilinx) to generate RAM or ROM. Can you help me?

 

[Gordon Freeman]

On Apr 18, 4:47 pm, Matthias Alles <REMOVEallesCAPIT...@NOeit.SPAMuni-
kl.de> wrote:

Hi!

Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding
techniques. This chapter describes detailed which HDL constructs will
result in the usage of which FPGA resource.

Matthias

Gordon Freeman schrieb:

Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only
use slices resources. But I want to use BRam or DRam resources on FPGA
(FPGA's Xilinx) to generate RAM or ROM. Can you help me?

Thank you.
Right now, I can make it.