use alias in port declaration?

[Mike Dearman]

I have the following vector in my design:

signal CONTROL_PINS : std_logic_vector(69 downto 0);

I want to connect certain bits of this vector to pins, and i want to
give them meaningfull names, for example i want a pin called "ABC"
connected to CONTROL_PINS(4)

the most obvious thing i can think of is to use an alias:

alias "ABC" is CONTROL_PINS(4);

but i can't use "ABC" in the port declaration as it then complains
about being declared twice.

Am i going about this the wrong way? Suggestions welcomed

Mike

 

[KJ]

On Feb 26, 12:46 pm, Mike Dearman <m...@michaeldearman.com> wrote:

I have the following vector in my design:

signal  CONTROL_PINS                    : std_logic_vector(69 downto 0);

I want to connect certain bits of this vector to pins, and i want to
give them meaningfull names, for example i want a pin called "ABC"
connected to CONTROL_PINS(4)

the most obvious thing i can think of is to use an alias:

alias "ABC" is CONTROL_PINS(4);

Is there some reason why simply adding the following assignment in the
architecture is not acceptable?

ABC <= CONTROL_PINS(4);

It delays ABC by one simulation delta which can bite you if ABC is
then used as some form of clock downstream and the thing being sample
is not similarly delta delayed, but other than that...

KJ

 

[Mike Dearman]

On 26 Feb, 21:03, KJ <kkjenni...@sbcglobal.net> wrote:

On Feb 26, 12:46 pm, Mike Dearman <m...@michaeldearman.com> wrote:

I have the following vector in my design:

signal  CONTROL_PINS                    : std_logic_vector(69 downto 0);

I want to connect certain bits of this vector to pins, and i want to
give them meaningfull names, for example i want a pin called "ABC"
connected to CONTROL_PINS(4)

the most obvious thing i can think of is to use an alias:

alias "ABC" is CONTROL_PINS(4);

Is there some reason why simply adding the following assignment in the
architecture is not acceptable?

ABC <= CONTROL_PINS(4);

It delays ABC by one simulation delta which can bite you if ABC is
then used as some form of clock downstream and the thing being sample
is not similarly delta delayed, but other than that...

KJ

They're bi-directional signals and i understood <= is a directional
assignment?

sorry, i should have mentioned the bi-directional thing in the
original post.

Mike

 

[Jonathan Bromley]

On Fri, 27 Feb 2009 00:48:50 -0800 (PST), Mike Dearman wrote:

I have the following vector in my design:

signal  CONTROL_PINS                    : std_logic_vector(69 downto 0);

I want to connect certain bits of this vector to pins, and i want to
give them meaningfull names, for example i want a pin called "ABC"
connected to CONTROL_PINS(4)
[...]
sorry, i should have mentioned the bi-directional thing in the
original post.

I don't think there is any way in VHDL to do exactly what
you are asking. Verilog has the concept of "port expressions"
which allow you to map a named port to a different-named
signal inside the module, but VHDL can't do that.

However, you can get very much the same effect either with
components and configurations or with a wrapper entity.

Suppose you have

entity UsesVector;
port (V: inout std_logic_vector(3 downto 0);
end;

but you would prefer it to look like this:

entity NamedPorts;
port (V3: inout std_logic;
V21: inout std_logic_vector(1 downto 0);
V0: inout std_logic);
end;

then all you need is

architecture Wrapper of NamedPorts is
begin
guts: entity work.UsesVector
port map (V(3) => V3,
V(2 downto 1) => V21,
V(0) => V0 );
end;

Somewhat messy, but easy to do.

Hope this helps - sorry it's so late.
--
Jonathan Bromley, Consultant

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