Use a variable index to assign sections of a bus

[bl]

I would like to create a parameterized synthsizeable piece of code in
verilog or system verilog to assign a vector
a section of the vector using a variable as the index.

Consider the following snippet:

integer index, index_base;
parameter max = 4;

for (index_base = 0; index_base<max; index_base = index_base+1)
begin
vector_out = vector_in
[((index_base + 1)*max-1): (index_base*max)]
end

The code above is not acceptable code as a part of the bus cannot be
extracted in this manner as the indices are not
constants while extracting several bits. However, if one were indexing
through it a bit at a time the simulators support
it.

I could get around it by changing it to the following:

for (index_base = 0; index_base<max; index_base = index_base+1)
begin

for (index = 0; index < max; index = index + 1)
begin
vector_out[index] = vector_in[(index_base*max)+ index];
end
end

This works but gets cumbersome and less readable. Is there a construct
in verilog 2k or system verilog that is less convoluted.

Thanks

bl

 

bl wrote:

I would like to create a parameterized synthsizeable piece of code in
verilog or system verilog to assign a vector
a section of the vector using a variable as the index.

Consider the following snippet:

integer index, index_base;
parameter max = 4;

for (index_base = 0; index_base<max; index_base = index_base+1)
begin
vector_out = vector_in
[((index_base + 1)*max-1): (index_base*max)]
end

The code above is not acceptable code as a part of the bus cannot be
extracted in this manner as the indices are not
constants while extracting several bits. However, if one were indexing
through it a bit at a time the simulators support
it.

I could get around it by changing it to the following:

for (index_base = 0; index_base<max; index_base = index_base+1)
begin

for (index = 0; index < max; index = index + 1)
begin
vector_out[index] = vector_in[(index_base*max)+ index];
end
end

This works but gets cumbersome and less readable. Is there a construct
in verilog 2k or system verilog that is less convoluted.

Verilog 2001 introduced the hideous "indexed part select" which is
designed to help with your problem.

vect[base_expr +: width_expr]
vect[base_expr -: width_expr]

width_expr must be a compile-time constant. The semantics vary
slightly depending on whether vect was declared with an ascending or
descending range.


This probably isn't useful either, as your synth tool may not support
it.

BTW, there was nothing inherently wrong with your original solution -
the equivalent in VHDL will simulate and synthesise just fine. Not
allowing it to be acceptable Verilog allows the tool writers to make
some short cuts that probably don't help contemporary compilers at all,
but are quite effective for annoying people who actually have to use
the language.

Sorry about the rant. I'm a bit fed up with language misfeatures at
the moment.

Regards,
Allan