USB vhdl code (followup)

[Rob Maris]

Since no followups of elder messages seems to be possible, I started
this as new message.

Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL.

A student of my university has created a USB 1.1 IP in VHDL.

Rob

 

[Martin Maurer]

A student of my university has created a USB 1.1 IP in VHDL.

Possible to get this code ?

Regards,

Martin

 

[Don Golding]

I would like to see the code too...

Thanks,
Don

"Martin Maurer" <capiman@clibb.de> wrote in message
news:cf0e8t$3jj$04$1@news.t-online.com...

A student of my university has created a USB 1.1 IP in VHDL.

Possible to get this code ?

Regards,

Martin

 

[Alex Gibson]

"Rob Maris" <maris@fh-aachen.de> wrote in message
news:dced596e.0408060129.6cdbf414@posting.google.com...

Since no followups of elder messages seems to be possible, I started
this as new message.

Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL.

A student of my university has created a USB 1.1 IP in VHDL.

Rob

Are you guys going to add it to opencores.org ?