USB 2.0 controller using ISP1581 device

[Om]

Hello guys,

I have been implementing a high speed controller for USB 2.0
communication on Xilinx VirtexII FPGA, which interfaces to USB bus
through Philips ISP1581 device. I don't know how to go about it as I'm
a very new to USB stuffs.

I have got a choice of using MicroBlaze softcore microprocessor, but
currently, I'm encountering lots of trouble downloading it onto the
FPGA using already written C-code for ISP1581 device.

So, I would be grateful if you could be able to give me some
suggestions or directions on how to go about it. I wonder, if USB 2.0
core is available for ISP1581 device.

Thanks,
Om

 

[Antti Lukats]

gupt0009@flinders.edu.au (Om) wrote in message news:<b87a9948.0310191846.8a4d786@posting.google.com>...

Hello guys,

I have been implementing a high speed controller for USB 2.0
communication on Xilinx VirtexII FPGA, which interfaces to USB bus
through Philips ISP1581 device. I don't know how to go about it as I'm
a very new to USB stuffs.

I have got a choice of using MicroBlaze softcore microprocessor, but
currently, I'm encountering lots of trouble downloading it onto the
FPGA using already written C-code for ISP1581 device.

where is the problem?
have you connected it successfully to microlaze PLB bus?

So, I would be grateful if you could be able to give me some
suggestions or directions on how to go about it. I wonder, if USB 2.0
core is available for ISP1581 device.

there is no need for USB core for ISP1581 as IS1581 is the core!
you only need interfaces to ISP1581 to access from microblaze and posssible
use DMA

 

[Om]

Hello Antti,
Thanks for answering to my queries. I wonder if you could help me with
this. Here is my problems.

The C-code, I got, is written for parallel interfacing with ISP1581. I
wonder, if I have to modify my code to use it as GPIO pins in
Microblaze. I still haven't got clear understanding of configuring
Microblaze. I have been using EDK 3.2 and ISE 5.2. And I also need to
setup temporary SRAM and its controller on FPGA so that the data
communication could be established between PC and SRAM through USB. If
you have any suggestion or experience relating this, please pass it
on.

Thanks,
Om


antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0310192220.1a854dc7@posting.google.com>...

gupt0009@flinders.edu.au (Om) wrote in message news:<b87a9948.0310191846.8a4d786@posting.google.com>...
I have been implementing a high speed controller for USB 2.0
communication on Xilinx VirtexII FPGA, which interfaces to USB bus
through Philips ISP1581 device. I don't know how to go about it as I'm
a very new to USB stuffs.

I have got a choice of using MicroBlaze softcore microprocessor, but
currently, I'm encountering lots of trouble downloading it onto the
FPGA using already written C-code for ISP1581 device.

where is the problem?
have you connected it successfully to microlaze PLB bus?

So, I would be grateful if you could be able to give me some
suggestions or directions on how to go about it. I wonder, if USB 2.0
core is available for ISP1581 device.

there is no need for USB core for ISP1581 as IS1581 is the core!
you only need interfaces to ISP1581 to access from microblaze and posssible
use DMA

 

[Antti Lukats]

Hello Antti,
Thanks for answering to my queries. I wonder if you could help me with
this. Here is my problems.

The C-code, I got, is written for parallel interfacing with ISP1581. I
wonder, if I have to modify my code to use it as GPIO pins in
Microblaze. I still haven't got clear understanding of configuring
Microblaze. I have been using EDK 3.2 and ISE 5.2. And I also need to
setup temporary SRAM and its controller on FPGA so that the data
communication could be established between PC and SRAM through USB. If
you have any suggestion or experience relating this, please pass it on.

as quick start you can connect ISP1581 to GPIO pins and emulated a the
data control address bus. you just have to write some c routines that
access the isp1581 registers, by toggling gpio pins) thats easisest
for start and quick test.

for real application it would be preferred to write a xilin PLB IP core
that talks to isp1581, but software wise it want change anything.
You may leave it for later as it usually isnt without problems
custome PLB peripherals often dont work at the beginning...

same with shared RAM or whatever you decide to use, two options
you create a peripheral core, or you use ISE as toplevel, this
is also not without caveats, works but only if you do many many
step in row and all precise correct. then you can write portion
of the design in verilog/vhdl and use microblaze SOC as schematic
component in ISE

antti