Usage of $input

[kb33]

Hi,

I am trying to make my test bench read commands from a file using the
$input system task. But simply adding this command along with the file
name (that has the commands to run) doesn't seem to be working in
Modelsim. The simulator complains that "System task or function $input
is not defined". This is the Modelsim PE Student Edition 6.3a. What am
I doing wrong?

Thanks
Kanchan

 

[mrfirmware]

On Oct 3, 1:51 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

Hi,

I am trying to make my test bench read commands from a file using the
$input system task. But simply adding this command along with the file
name (that has the commands to run) doesn't seem to be working in
Modelsim. The simulator complains that "System task or function $input
is not defined". This is the Modelsim PE Student Edition 6.3a. What am
I doing wrong?

I'm unfamiliar (and new to Verilog) but I successfully use the
following construct to get data from a file:

if ($value$plusargs("my_in_file=%s", in_file) == 0) begin
$display("** Error: No input file specified in call to vsim,
don't know what file to open.");
$finish(0);
end

fd = $fopen(in_file, "r");
fc = $fgets(line, fd);
// parse 'line'.
$fclose(fd);

To set 'my_in_file' I invoke vsim something like this:

vsim +my_in_file=/tmp/foo.txt ...

- Mark

 

[kb33]

On Oct 3, 2:40 pm, mrfirmware <mrfirmw...@gmail.com> wrote:

On Oct 3, 1:51 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

Hi,

I am trying to make my test bench read commands from a file using the
$input system task. But simply adding this command along with the file
name (that has the commands to run) doesn't seem to be working in
Modelsim. The simulator complains that "System task or function $input
is not defined". This is the Modelsim PE Student Edition 6.3a. What am
I doing wrong?

I'm unfamiliar (and new to Verilog) but I successfully use the
following construct to get data from a file:

if ($value$plusargs("my_in_file=%s", in_file) == 0) begin
$display("** Error: No input file specified in call to vsim,
don't know what file to open.");
$finish(0);
end

fd = $fopen(in_file, "r");
fc = $fgets(line, fd);
// parse 'line'.
$fclose(fd);

To set 'my_in_file' I invoke vsim something like this:

vsim +my_in_file=/tmp/foo.txt ...

- Mark

Hi Mark,
Are you talking about data or commands? I am specifically interested
in executing commands that are in another input file. Does this work
in that case as well?

 

[mrfirmware]

On Oct 3, 2:44 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

On Oct 3, 2:40 pm, mrfirmware <mrfirmw...@gmail.com> wrote:



On Oct 3, 1:51 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

Hi,

I am trying to make my test bench read commands from a file using the
$input system task. But simply adding this command along with the file
name (that has the commands to run) doesn't seem to be working in
Modelsim. The simulator complains that "System task or function $input
is not defined". This is the Modelsim PE Student Edition 6.3a. What am
I doing wrong?

I'm unfamiliar (and new to Verilog) but I successfully use the
following construct to get data from a file:

if ($value$plusargs("my_in_file=%s", in_file) == 0) begin
$display("** Error: No input file specified in call to vsim,
don't know what file to open.");
$finish(0);
end

fd = $fopen(in_file, "r");
fc = $fgets(line, fd);
// parse 'line'.
$fclose(fd);

To set 'my_in_file' I invoke vsim something like this:

vsim +my_in_file=/tmp/foo.txt ...

- Mark

Hi Mark,
Are you talking about data or commands? I am specifically interested
in executing commands that are in another input file. Does this work
in that case as well?

I'm not sure I follow. What do you mean 'commands'? Commands for VSIM
to interpret or your own testbench? I'm talking about your own test
bench. You need to use a .do file and write Tcl with VSIM extensions
to control VSIM programatically (for the most part).
--
- Mark

 

[kb33]

On Oct 3, 3:25 pm, mrfirmware <mrfirmw...@gmail.com> wrote:

On Oct 3, 2:44 pm, kb33 <kanchan.devarako...@gmail.com> wrote:



On Oct 3, 2:40 pm, mrfirmware <mrfirmw...@gmail.com> wrote:

On Oct 3, 1:51 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

Hi,

I am trying to make my test bench read commands from a file using the
$input system task. But simply adding this command along with the file
name (that has the commands to run) doesn't seem to be working in
Modelsim. The simulator complains that "System task or function $input
is not defined". This is the Modelsim PE Student Edition 6.3a. What am
I doing wrong?

I'm unfamiliar (and new to Verilog) but I successfully use the
following construct to get data from a file:

if ($value$plusargs("my_in_file=%s", in_file) == 0) begin
$display("** Error: No input file specified in call to vsim,
don't know what file to open.");
$finish(0);
end

fd = $fopen(in_file, "r");
fc = $fgets(line, fd);
// parse 'line'.
$fclose(fd);

To set 'my_in_file' I invoke vsim something like this:

vsim +my_in_file=/tmp/foo.txt ...

- Mark

Hi Mark,
Are you talking about data or commands? I am specifically interested
in executing commands that are in another input file. Does this work
in that case as well?

I'm not sure I follow. What do you mean 'commands'? Commands for VSIM
to interpret or your own testbench? I'm talking about your own test
bench. You need to use a .do file and write Tcl with VSIM extensions
to control VSIM programatically (for the most part).
--
- Mark

Putting it more simply, lets say you have the following instructions
in your testbench (I am skipping the definitions of the various
signals..)


initial
begin
//Initialization....

sys_clk <= 0;
reset_n <= 0;
sig_a <= 1;
sig_b <= 0;

#(2*period)
reset_n <= 1;

#(55*period);
begin
sig_a <= 8;
sig_b <= 10;
end

#(1*period)
sig_a <= 4;

#(100*period) $finish;
end

Usually, you would just have these statements in your testbench. But
if you do not want these statements in your testbench, but instead
want to put them in another text file that your testbench can open and
read using a system task or function, how would you do that? If
possible, I want to do it without any Tcl commands or anything outside
of my testbench. That is the reason I inquired about the usage of the
$input command (from inside the testbench).

Kanchan

 

[John_H]

"kb33" <kanchan.devarakonda@gmail.com> wrote in message
news:1191446366.756948.31550@22g2000hsm.googlegroups.com...

Putting it more simply, lets say you have the following instructions
in your testbench (I am skipping the definitions of the various
signals..)


initial
begin
//Initialization....

sys_clk <= 0;
reset_n <= 0;
sig_a <= 1;
sig_b <= 0;

#(2*period)
reset_n <= 1;

#(55*period);
begin
sig_a <= 8;
sig_b <= 10;
end

#(1*period)
sig_a <= 4;

#(100*period) $finish;
end

Usually, you would just have these statements in your testbench. But
if you do not want these statements in your testbench, but instead
want to put them in another text file that your testbench can open and
read using a system task or function, how would you do that? If
possible, I want to do it without any Tcl commands or anything outside
of my testbench. That is the reason I inquired about the usage of the
$input command (from inside the testbench).

Kanchan

How about

'include "myInitFile.v"

 

[mrfirmware]

On Oct 3, 5:19 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

On Oct 3, 3:25 pm, mrfirmware <mrfirmw...@gmail.com> wrote:



On Oct 3, 2:44 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

On Oct 3, 2:40 pm, mrfirmware <mrfirmw...@gmail.com> wrote:

On Oct 3, 1:51 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

Hi,

I am trying to make my test bench read commands from a file using the
$input system task. But simply adding this command along with the file
name (that has the commands to run) doesn't seem to be working in
Modelsim. The simulator complains that "System task or function $input
is not defined". This is the Modelsim PE Student Edition 6.3a. What am
I doing wrong?

I'm unfamiliar (and new to Verilog) but I successfully use the
following construct to get data from a file:

if ($value$plusargs("my_in_file=%s", in_file) == 0) begin
$display("** Error: No input file specified in call to vsim,
don't know what file to open.");
$finish(0);
end

fd = $fopen(in_file, "r");
fc = $fgets(line, fd);
// parse 'line'.
$fclose(fd);

To set 'my_in_file' I invoke vsim something like this:

vsim +my_in_file=/tmp/foo.txt ...

- Mark

Hi Mark,
Are you talking about data or commands? I am specifically interested
in executing commands that are in another input file. Does this work
in that case as well?

I'm not sure I follow. What do you mean 'commands'? Commands for VSIM
to interpret or your own testbench? I'm talking about your own test
bench. You need to use a .do file and write Tcl with VSIM extensions
to control VSIM programatically (for the most part).
--
- Mark

Putting it more simply, lets say you have the following instructions
in your testbench (I am skipping the definitions of the various
signals..)

initial
begin
//Initialization....

sys_clk <= 0;
reset_n <= 0;
sig_a <= 1;
sig_b <= 0;

#(2*period)
reset_n <= 1;

#(55*period);
begin
sig_a <= 8;
sig_b <= 10;
end

#(1*period)
sig_a <= 4;

#(100*period) $finish;
end

Usually, you would just have these statements in your testbench. But
if you do not want these statements in your testbench, but instead
want to put them in another text file that your testbench can open and
read using a system task or function, how would you do that? If
possible, I want to do it without any Tcl commands or anything outside
of my testbench. That is the reason I inquired about the usage of the
$input command (from inside the testbench).

Well that's a very different thing then, once you're in the simulator
it's too late to "execute" new Verilog at run-time. You need to
compile the stuff, so as John_H said, use `include. You might just
look a breaking up blocks of procedural code into functions and tasks
and then calling them from your initial block. Or you could do both,
put functions and tasks in another file and `include it.
--
- Mark

 

kb33 wrote:

Usually, you would just have these statements in your testbench. But
if you do not want these statements in your testbench, but instead
want to put them in another text file that your testbench can open and
read using a system task or function, how would you do that? If
possible, I want to do it without any Tcl commands or anything outside
of my testbench. That is the reason I inquired about the usage of the
$input command (from inside the testbench).

You cannot just read in Verilog code at run-time, at least not in a
compiled-code simulator. Verilog code has to be compiled with the
rest of your design. It is possible that a simulator that uses an
interpreter could read Verilog code at run-time, but that is not what
you are using.

You could write a Verilog testbench that read in data from a text file
(using $readmem or $fscanf) and applied it to the design. But it is
unlikely that you would make the text file use Verilog syntax, since
then your testbench would have to be complex enough to interpret a
significant subset of Verilog syntax.

 

[kb33]

You cannot just read in Verilog code at run-time, at least not in a
compiled-code simulator. Verilog code has to be compiled with the
rest of your design. It is possible that a simulator that uses an
interpreter could read Verilog code at run-time, but that is not what
you are using.

SO as I understand from the above discussion, if we have a file
(containing Verilog style execution commands) that is dynamically
changing during simulation, there is no way to read it periodically
from inside a testbench, because simulator cannot execute Verilog code
at run-time, correct?
Any work-around to this problem?

Kanchan

 

[John_H]

kb33 wrote:
<snip>

Any work-around to this problem?

Kanchan

I don't see that it's a problem.
Your vision of dynamically swapping code seems unusual at best. What
could you possibly gain from this "feature?"

 

[kb33]

On Oct 3, 11:10 pm, John_H <newsgr...@johnhandwork.com> wrote:

kb33 wrote:

snip

Any work-around to this problem?

Kanchan

I don't see that it's a problem.
Your vision of dynamically swapping code seems unusual at best. What
could you possibly gain from this "feature?"

I am trying to combine a software application with my hardware module.
For this purpose, I need them to communicate with other (since the
output of one is the input to another and vice versa). I don't know if
it is a very primitive way of implementing, but I thought that if I
could write the output of my DUT (which I know how to using $monitor
etc.), the software application could read it; and then if there was a
way to read the response of the software application during run-time
(from a text file opened inside the testbench), I could perform the
next step in my simulation. The software application, of course,
writes its response in the form of verilog commands with the
appropriate stimuli for the DUT.

Kanchan

 

[Evan Lavelle]

On Thu, 04 Oct 2007 03:44:27 -0000, kb33
<kanchan.devarakonda@gmail.com> wrote:

The software application, of course,
writes its response in the form of verilog commands with the
appropriate stimuli for the DUT.

This is the bit you need to change. Both your testbench and your
"software application" are just bits of software that need to talk to
each other.

You need to define a communications protocol between the two halves.
You can have a client/server model, for example, with the two halves
talking over sockets, or something simpler, like the file exchange
you're talking about (but file exchange is probably going to be far
too restricting for any serious use).

This can get pretty complicated, so you should think about it some
more and ask more specific questions. At the bottom level in your
Verilog testbench, though, you'll have to write some code which
responds to incoming command (which might just be single-byte tokens,
for example), and which then executes the "verilog commands" you're
talking about.

Evan

 

[Chris F Clark]

kb33 <kanchan.devarakonda@gmail.com> writes:

I am trying to combine a software application with my hardware module.
For this purpose, I need them to communicate with other (since the
output of one is the input to another and vice versa).

Software applications like this are often called "foreign models".
The normal way to communicate between a software application and a
testbench is to use PLI (or VPI) calls from within the application.
Such calls allow the application to read and write the values of the
Verilog in the testbench (and do other relevant things). These
interfaces (PLI and VPI) were specifically defined to allow you to do
what you want to do.

Hope this helps,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

[mrfirmware]

On Oct 3, 11:44 pm, kb33 <kanchan.devarako...@gmail.com> wrote:

On Oct 3, 11:10 pm, John_H <newsgr...@johnhandwork.com> wrote:

kb33 wrote:

snip

Any work-around to this problem?

Kanchan

I don't see that it's a problem.
Your vision of dynamically swapping code seems unusual at best. What
could you possibly gain from this "feature?"

I am trying to combine a software application with my hardware module.
For this purpose, I need them to communicate with other (since the
output of one is the input to another and vice versa). I don't know if
it is a very primitive way of implementing, but I thought that if I
could write the output of my DUT (which I know how to using $monitor
etc.), the software application could read it; and then if there was a
way to read the response of the software application during run-time
(from a text file opened inside the testbench), I could perform the
next step in my simulation. The software application, of course,
writes its response in the form of verilog commands with the
appropriate stimuli for the DUT.

I did this with DPI and SystemVerilog. I had my SV testbench call my C
TCP/IP listener/command processor code. Then I wrote a Perl client
(easy to parse text etc) to connect up to the TCP/IP listener which
would call back into the SV testbench tasks and functions based upon
what the client told the listener to do.

Then I decided SV is rich enough to code the file processing, parsing,
and writing directly into an SV class in a package so I dispensed with
the whole client/server thing.

You could also check out MyHDL (http://myhdl.jandecaluwe.com/doku.php/
start) although I've never tried this, it looks pretty interesting.
--
- Mark

 

[mmintz@gmail.com]

Hi Kanchan,

You might want to consider the open source code called Teal I wrote to
connect C/C++ with Verilog in a clean way.

It's at www.trusster.com and is used by many companies.

Your software should be limited to register access and interrupt
handling. Teal has a memory::read(int, int*) and memory::write(int,
int) type of interface. You need to write a bfm to "talk" the
hardware's wire protocol.

Teal also provides a at (wire) call that stops a thread until the wire
changes. You use that for interrupt handling.

Other than that, you need to wrap your "main()" into a function that
teal calls.

Good Luck!

-Mike

On Oct 4, 11:44 am, mrfirmware <mrfirmw...@gmail.com> wrote:

On Oct 3, 11:44 pm, kb33 <kanchan.devarako...@gmail.com> wrote:



On Oct 3, 11:10 pm, John_H <newsgr...@johnhandwork.com> wrote:

kb33 wrote:

snip

Any work-around to this problem?

Kanchan

I don't see that it's a problem.
Your vision of dynamically swapping code seems unusual at best. What
could you possibly gain from this "feature?"

I am trying to combine a software application with my hardware module.
For this purpose, I need them to communicate with other (since the
output of one is the input to another and vice versa). I don't know if
it is a very primitive way of implementing, but I thought that if I
could write the output of my DUT (which I know how to using $monitor
etc.), the software application could read it; and then if there was a
way to read the response of the software application during run-time
(from a text file opened inside the testbench), I could perform the
next step in my simulation. The software application, of course,
writes its response in the form of verilog commands with the
appropriate stimuli for the DUT.

I did this with DPI and SystemVerilog. I had my SV testbench call my C
TCP/IP listener/command processor code. Then I wrote a Perl client
(easy to parse text etc) to connect up to the TCP/IP listener which
would call back into the SV testbench tasks and functions based upon
what the client told the listener to do.

Then I decided SV is rich enough to code the file processing, parsing,
and writing directly into an SV class in a package so I dispensed with
the whole client/server thing.

You could also check out MyHDL (http://myhdl.jandecaluwe.com/doku.php/
start) although I've never tried this, it looks pretty interesting.
--
- Mark