Urgent : verilog +protect does not work with `include file

[aspiring_enterprenur]

I am trying to protect some verilog code and I can 't seem to protect
it if the code includes a 'define' defined in another file. I am using
verilog-xl and using the following command

verilog +protect design1.v

The design1.v has an include file that is the same directory that i am
trying to run the verilog command from.

Has anyone faced similar problems ? It works on VCS and Modelsim but
Verilog-XL has a issues, maybe there is something i am not doing right.

My file looks something like this :

module design1;

`include defines.h

`protect

// Lines of Code

`endprotect

endmodule

 

[Ajeetha]

Hi,
I don't have VXL, but a thought: How about generating tokens.v from
VCS (-Xman option) and then use VXL to protect - essentially make a
single file (with no includes) and then try.

HTH
Ajeetha
www.noveldv.com

 

[aspiring_enterprenur]

Ajeetha,

Thanks for the valuable suggestion I think this should solve my
problem.

-Rohan

 

[Ira Baxter]

"aspiring_enterprenur" <rohanhubli@gmail.com> wrote in message
news:1132293441.744431.248780@g47g2000cwa.googlegroups.com...

I am trying to protect some verilog code and I can 't seem to protect
it if the code includes a 'define' defined in another file.

Google for "Verilog Obfuscator".

-- IDB