Urgent Question.

[Amit]

Hello,

I'm writing a test bench. However, I'm having to *.vhd files. What is
the syntax for the test bench when you have two or more entities?

Should I conisder all inputs and outputs of both entities in my test
bench?

Let's say I have:

--en1 is the transmitter part of UART
entity en1 is
port(x, clock, reset: in std_logic;
z1 : out std_logic);
end;

--en2 is the receiver part of UART
entity en2 is
port(y, clock, Enable: in std_logic;
z2 : out std_logic);
end;

and en1 is connected to en2. Is the following test bench component
correct?
should I consider all inputs and outputs of the UART in the component
definitin in test bench architecutre?

Regars,
Amit

 

[Mike Treseler]

Amit wrote:

I'm writing a test bench. However, I'm having to *.vhd files. What is
the syntax for the test bench when you have two or more entities?

That's up to the designer.
See the reference testbench here
http://home.comcast.net/~mike_treseler/

for testbench example using a single direct
instance of the uart UUT.


-- Mike Treseler