URGENT HELP!!! I NEED A PROJECT MADE IN VHDL FOR SIGNAL GENE

T

tudormarchis

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URGENT HELP!!! I NEED A PROJECT MADE IN VHDL FOR SIGNAL GENERATION ON
FPGA.....

please world help meeeee
 
tudormarchis a écrit :
URGENT HELP!!! I NEED A PROJECT MADE IN VHDL FOR SIGNAL GENERATION ON
FPGA.....

please world help meeeee
How much are you ready to pay for it ?

Nicolas
 
On Feb 6, 4:55 pm, "tudormarchis" <tudormarc...@yahoo.com> wrote:
URGENT HELP!!! I NEED A PROJECT MADE IN VHDL FOR SIGNAL GENERATION ON
FPGA.....

please world help meeeee
Connect the ouput of an oscillator to a clock input of a FPGA. Inside
the FPGA create a counter. Connect the counter's outputs to pins of
the FPGA. If you don't understand this, then read books on digital
hardware design.
BTW, the first step in making this generator (or any other "thing")
is to decide _what_ the signal generator (or "thing") should do! Ask
your professor for the specs! sheesh!

-Dave Pollum
 

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