H
Harika Suram
Guest
can anybody lookover this code and tell me where the error is
`timescale 1ns/1ps// time units for display of the outputs
//Declare the division module
module my_div(remainder,ready,done, word1, word2, start, clock,
reset);
//The length of the words to be used (32 bits)
parameter L_word=32;
parameter L_cnt=31;
//Module outputs
output [2*L_word-1 : 0] remainder;
output ready;
output done;
//Module inputs
input [L_word-1:0] word1;
input [L_word-1:0] word2;
input start;
input clock;
input reset;
reg empty;
wire flush; wire load_word; wire shift;
wire add_shift; wire increment;
wire [L_cnt-1:0] counter;
wire done=(counter==L_word || empty);
always@(word1 or word2)
if (word1==0 || word2==0)
empty = 1'b1;
else
empty = 1'b0;
datapath_division M_datapath(remainder, word1, word2, clock, reset,
flush, load_word, shift, fine, restore, increment, counter);
controller_division M_controller(remainder, ready, start, clock,
reset, empty, flush, load_word, shift, fine, restore, increment,
counter);
endmodule
//datapath Module
module datapath_division(remainder, word1, word2, clock, reset,
flush, ,run,load_word, shift, fine, restore, increment, counter);
parameter L_word=32;
parameter L_cnt=31;
output [2*L_word : 0] remainder;
reg[2*L_word-1 : 0] remainder=0;
input [L_word-1:0] word1;
input [L_word-1:0] word2;
input clock;
input flush;
input reset;
input load_word;
input shift;
input run;
input fine;
input restore;
input increment;
output [L_cnt-1:0] counter;
reg[L_cnt-1:0] counter=0;
reg[L_word-1:0] divisor;
//Datapath operations here
//Triggered by positive-going transition of clock or reset
always@(posedge clock or posedge reset)
//Set all parameters to zero if the operation is
"reset"
if (reset)
begin
divisor <=0;
remainder <=0;
counter <=0;
end
else
begin
//Set product to zero
if the operation is "flush"
if(flush) remainder<=0;
//Set parameters to passed values if operation is
"Load_word"
if (load_word)
begin
divisor <= word1;
remainder <={1'b0,word2}<<1;
counter
<=0;
if(run)
begin
remainder<={remainder[2*L_word:L_word]
divisor,remainder[L_word-1:0]};
end
end
// Add the divisor to the left
half of the remainder and place the result in the remainder if the
operation is restore
if(restore)
begin
remainder <= {remainder[2*L_word:L_word] + divisor,
remainder[L_word-1:0]} <<1;
remainder[0]<=1'b0;
end
//just shift the remainder if the operation is
shift
if(shift)
begin
remainder <= (remainder<<1);
remainder[0]<=1'b1;
//if the operation is increment then add one to the counter
end
if(increment)
counter <= counter + 1;
if(fine)
remainder <= remainder[2*L_word:L_word]>>1;
end
endmodule
//Controller logic
module controller_division(remainder, ready, start, clock, run, reset,
empty, flush, load_word, shift, fine, restore, increment, counter);
parameter L_word=4;
parameter L_cnt=3;
output ready;
input start;
input clock;
input reset;
input empty;
input [2*L_word-1 : 0] remainder;
output fine; reg fine;
output run; reg run;
output flush; reg flush;
output load_word; reg load_word;
output shift; reg shift;
output restore; reg restore;
output increment; reg increment;
input [L_cnt-1:0] counter;
reg state;
reg next_state;
parameter S_idle=0, S_running=1; // state encoding
wire ready = (state==S_idle) && (!reset);
//Triggered by positive going transition of clock or reset
always@(posedge clock or posedge reset)
if (reset) state<=S_idle;
else state<=next_state; // state transition
//When any of: state, start, Empty, product or counter changes
//This logic is run
always@(state or start or empty or remainder or counter)
begin
//initialize all outputs at the start
flush =0; load_word=0; shift=0; add_shift=0; increment =0; fine=0;
run=0;
// set according to the state
case (state)
//If state is S_Idle and it is not just
starting, then the next state is S_Idle
S_idle:
if(!start) next_state = S_idle;
else if (empty)
begin
flush = 1;
next_state = S_idle;
end
//Else load the words and
the next state is the running state to enable setting of the current
values
else if (start)
begin
load_word =1;
next_state=S_running;
run=1;
end
//In between start and end/Idle there is the running state
S_running:
begin
run=1;
increment =1;
//If the remainder is less than zero then then restore the value by
adding the divisor to the left half of the remainder and place the
result in the remainder
if(remainder[63]) restore=1;
//Else just shift the remainder
else shift=1;
if(counter==L_word-1)
begin
fine=1;
next_state=S_idle;
end
else
begin
next_state=S_running;
end
end
default:
next_state=S_idle;
endcase
end
endmodule
TESTBENCH
`timescale 1ns / 1ps//time units for display of the outputs
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:04:07 04/14/2010
// Design Name: my_div
// Module Name: C:/Xilinx/mult/multiplier/t_my_div.v
// Project Name: multiplier
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: my_div
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Declare division testbench
module t_my_div;
//we shall be using 32 bit long words
parameter L_word = 32;
wire [2*L_word-1:0] remainder;
wire ready;
reg [L_word-1:0] word1,word2;
reg start,clk,rst;
my_div
d1(.remainder(remainder),.ready(ready),.done(done),.word1(word1),.word2(word2),.start(start), .clock(clk), .reset(rst));
initial begin
start = 0;
clk = 0;
rst = 1;
//the words to be multiplied
//change values here
#100 word1= 32'd4;
#100 word2= 32'd6;
#10 rst = 0;
#5 start =1;
#100 start = 0;
#400 $finish;
end
always
begin
#5 clk = ~clk;
end
endmodule
This is my code for 32-bit division. when I am trying to synthesis Iam
getting an error as below
R:Xst:528 - Multi-source in Unit <my_div> on signal <counter<30>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<29>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<28>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<27>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<26>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<25>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<24>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<23>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<22>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<21>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<20>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<19>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<18>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<17>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<16>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<15>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<14>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<13>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<12>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<11>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<10>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<9>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<8>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<7>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<6>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<5>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<4>>;
this signal is connected to multiple drivers.
can someone tell me the solution for this
its very urgent
Thnkyou
`timescale 1ns/1ps// time units for display of the outputs
//Declare the division module
module my_div(remainder,ready,done, word1, word2, start, clock,
reset);
//The length of the words to be used (32 bits)
parameter L_word=32;
parameter L_cnt=31;
//Module outputs
output [2*L_word-1 : 0] remainder;
output ready;
output done;
//Module inputs
input [L_word-1:0] word1;
input [L_word-1:0] word2;
input start;
input clock;
input reset;
reg empty;
wire flush; wire load_word; wire shift;
wire add_shift; wire increment;
wire [L_cnt-1:0] counter;
wire done=(counter==L_word || empty);
always@(word1 or word2)
if (word1==0 || word2==0)
empty = 1'b1;
else
empty = 1'b0;
datapath_division M_datapath(remainder, word1, word2, clock, reset,
flush, load_word, shift, fine, restore, increment, counter);
controller_division M_controller(remainder, ready, start, clock,
reset, empty, flush, load_word, shift, fine, restore, increment,
counter);
endmodule
//datapath Module
module datapath_division(remainder, word1, word2, clock, reset,
flush, ,run,load_word, shift, fine, restore, increment, counter);
parameter L_word=32;
parameter L_cnt=31;
output [2*L_word : 0] remainder;
reg[2*L_word-1 : 0] remainder=0;
input [L_word-1:0] word1;
input [L_word-1:0] word2;
input clock;
input flush;
input reset;
input load_word;
input shift;
input run;
input fine;
input restore;
input increment;
output [L_cnt-1:0] counter;
reg[L_cnt-1:0] counter=0;
reg[L_word-1:0] divisor;
//Datapath operations here
//Triggered by positive-going transition of clock or reset
always@(posedge clock or posedge reset)
//Set all parameters to zero if the operation is
"reset"
if (reset)
begin
divisor <=0;
remainder <=0;
counter <=0;
end
else
begin
//Set product to zero
if the operation is "flush"
if(flush) remainder<=0;
//Set parameters to passed values if operation is
"Load_word"
if (load_word)
begin
divisor <= word1;
remainder <={1'b0,word2}<<1;
counter
<=0;
if(run)
begin
remainder<={remainder[2*L_word:L_word]
divisor,remainder[L_word-1:0]};
end
end
// Add the divisor to the left
half of the remainder and place the result in the remainder if the
operation is restore
if(restore)
begin
remainder <= {remainder[2*L_word:L_word] + divisor,
remainder[L_word-1:0]} <<1;
remainder[0]<=1'b0;
end
//just shift the remainder if the operation is
shift
if(shift)
begin
remainder <= (remainder<<1);
remainder[0]<=1'b1;
//if the operation is increment then add one to the counter
end
if(increment)
counter <= counter + 1;
if(fine)
remainder <= remainder[2*L_word:L_word]>>1;
end
endmodule
//Controller logic
module controller_division(remainder, ready, start, clock, run, reset,
empty, flush, load_word, shift, fine, restore, increment, counter);
parameter L_word=4;
parameter L_cnt=3;
output ready;
input start;
input clock;
input reset;
input empty;
input [2*L_word-1 : 0] remainder;
output fine; reg fine;
output run; reg run;
output flush; reg flush;
output load_word; reg load_word;
output shift; reg shift;
output restore; reg restore;
output increment; reg increment;
input [L_cnt-1:0] counter;
reg state;
reg next_state;
parameter S_idle=0, S_running=1; // state encoding
wire ready = (state==S_idle) && (!reset);
//Triggered by positive going transition of clock or reset
always@(posedge clock or posedge reset)
if (reset) state<=S_idle;
else state<=next_state; // state transition
//When any of: state, start, Empty, product or counter changes
//This logic is run
always@(state or start or empty or remainder or counter)
begin
//initialize all outputs at the start
flush =0; load_word=0; shift=0; add_shift=0; increment =0; fine=0;
run=0;
// set according to the state
case (state)
//If state is S_Idle and it is not just
starting, then the next state is S_Idle
S_idle:
if(!start) next_state = S_idle;
else if (empty)
begin
flush = 1;
next_state = S_idle;
end
//Else load the words and
the next state is the running state to enable setting of the current
values
else if (start)
begin
load_word =1;
next_state=S_running;
run=1;
end
//In between start and end/Idle there is the running state
S_running:
begin
run=1;
increment =1;
//If the remainder is less than zero then then restore the value by
adding the divisor to the left half of the remainder and place the
result in the remainder
if(remainder[63]) restore=1;
//Else just shift the remainder
else shift=1;
if(counter==L_word-1)
begin
fine=1;
next_state=S_idle;
end
else
begin
next_state=S_running;
end
end
default:
next_state=S_idle;
endcase
end
endmodule
TESTBENCH
`timescale 1ns / 1ps//time units for display of the outputs
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:04:07 04/14/2010
// Design Name: my_div
// Module Name: C:/Xilinx/mult/multiplier/t_my_div.v
// Project Name: multiplier
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: my_div
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Declare division testbench
module t_my_div;
//we shall be using 32 bit long words
parameter L_word = 32;
wire [2*L_word-1:0] remainder;
wire ready;
reg [L_word-1:0] word1,word2;
reg start,clk,rst;
my_div
d1(.remainder(remainder),.ready(ready),.done(done),.word1(word1),.word2(word2),.start(start), .clock(clk), .reset(rst));
initial begin
start = 0;
clk = 0;
rst = 1;
//the words to be multiplied
//change values here
#100 word1= 32'd4;
#100 word2= 32'd6;
#10 rst = 0;
#5 start =1;
#100 start = 0;
#400 $finish;
end
always
begin
#5 clk = ~clk;
end
endmodule
This is my code for 32-bit division. when I am trying to synthesis Iam
getting an error as below
R:Xst:528 - Multi-source in Unit <my_div> on signal <counter<30>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<29>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<28>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<27>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<26>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<25>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<24>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<23>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<22>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<21>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<20>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<19>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<18>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<17>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<16>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<15>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<14>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<13>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<12>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<11>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<10>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<9>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<8>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<7>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<6>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<5>>;
this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <my_div> on signal <counter<4>>;
this signal is connected to multiple drivers.
can someone tell me the solution for this
its very urgent
Thnkyou