uPDxxxxx chips datasheets (camcorder, vcr, etc)

[msg]

Does anyone have a repository of datasheets or at least valid signal
descriptions for uPD series chips used in Matsushita (Panasonic)
camcorders, vcrs, etc.?

Currently I am seeking data on the uPD9313G or uPD9313GB video sync
generator; the pin descriptions for this part, on a schematic in
a camcorder service manual, are incorrect, as evidenced by a block
diagram which labels the pins entirely differently (and also by
common sense).

The chip is totally unlike the LM1882 or 74ACT715 parts for which data
is available.

This particular manual contains no descriptions of operation of the
device and many pins connect to downstream proprietary devices so
deducing their function in context is unlikely. If one is to believe
the pin labeling in the block diagram however, a small number of
pins have standard outputs like Vertical and Horizontal Drive,
Blanking, Composite Sync, Clamp Pulse, but other abbreviations are
cryptic and to me unfamiliar. Scoping other output pins could yield
clues, but the inputs and programming pins are the mystery.

Unless this chip was produced for just one model of camcorder, it will
have some standard functions and inputs; I hope to learn how to genlock
it.

Michael

 

[larwe]

On Jun 24, 10:56 am, msg <msg@_cybertheque.org_> wrote:

Does anyone have a repository of datasheets or at least valid signal
descriptions for uPD series chips used in Matsushita (Panasonic)
camcorders, vcrs, etc.?

Well, if the PN starts with uPD or muPD they're NEC parts, for what
that's worth. How old is this piece of equipment?

 

[msg]

larwe wrote:

On Jun 24, 10:56 am, msg <msg@_cybertheque.org_> wrote:

Does anyone have a repository of datasheets or at least valid signal
descriptions for uPD series chips used in Matsushita (Panasonic)
camcorders, vcrs, etc.?


Well, if the PN starts with uPD or muPD they're NEC parts, for what
that's worth. How old is this piece of equipment?

Hi Lewin; thanks for your reply.

The machine is from 1987/88. I am reusing just the camera head, which
has rather impressive specs and can easily be used independently of
the main chassis and vcr deck, with a little wiring and glue logic.

Every chip that isn't a gate array in this machine has been assigned
a (mu)PD number, which suggests to me some intention of standardization,
but I may be dreaming.

Ergo, if NEC parts, can anyone lay hands on documents that may describe
my Sync Gen chip?

Thanks,

Michael

 

[msg]

cs_posting@hotmail.com wrote:

On Jun 24, 10:56 am, msg <msg@_cybertheque.org_> wrote:

Does anyone have a repository of datasheets or at least valid signal
descriptions for uPD series chips used in Matsushita (Panasonic)
camcorders, vcrs, etc.?


Unless this chip was produced for just one model of camcorder, it will
have some standard functions and inputs; I hope to learn how to genlock
it.


Do people actually genlock VTR's by servoing them to external sync?

Sure, all the time, but in my case I am only interested in the camera
section, which has the master timing generator in it.

I thought it was done using a time base corrector - which basically
captures and re-creates the signal. But I could be wrong.

Yes, for devices that can't be synced, that is a solution. But for
multiple cameras, the preferred approach is to genlock them.

Michael

 

On Jun 24, 10:56 am, msg <msg@_cybertheque.org_> wrote:

Does anyone have a repository of datasheets or at least valid signal
descriptions for uPD series chips used in Matsushita (Panasonic)
camcorders, vcrs, etc.?

Unless this chip was produced for just one model of camcorder, it will
have some standard functions and inputs; I hope to learn how to genlock
it.

Do people actually genlock VTR's by servoing them to external sync?

I thought it was done using a time base corrector - which basically
captures and re-creates the signal. But I could be wrong.

I'm not sure how much luck you will have unless some model in the
product line had this capability. Even if the timing of the video is
unrelated to the tape transport, this doesn't necessarily mean that
you have a means to reset the clock dividers to match something
external, or to keep it locked.

Conceptually speaking, if you had all the data sheets for a VGA card,
how would you genlock that? Replacing the clock generator with an
FPGA?

 

[larwe]

On Jun 24, 2:47 pm, msg <msg@_cybertheque.org_> wrote:

Every chip that isn't a gate array in this machine has been assigned
a (mu)PD number, which suggests to me some intention of standardization,
but I may be dreaming.

Wishful thinking, more like. I would say the appliance is based on a
reference design from NEC and hence the plethora of NEC parts; they're
all part of a single chipset. In fact I'd say the single-vendor
approach indicates more likely a /lack/ of standardization - it was
easier to get an all-NEC design working than to hybridize it

 

On Jun 24, 2:48 pm, msg <msg@_cybertheque.org_> wrote:

cs_post...@hotmail.com wrote:
On Jun 24, 10:56 am, msg <msg@_cybertheque.org_> wrote:

Does anyone have a repository of datasheets or at least valid signal
descriptions for uPD series chips used in Matsushita (Panasonic)
camcorders, vcrs, etc.?

Unless this chip was produced for just one model of camcorder, it will
have some standard functions and inputs; I hope to learn how to genlock
it.

Do people actually genlock VTR's by servoing them to external sync?

Sure, all the time, but in my case I am only interested in the camera
section, which has the master timing generator in it.

I thought it was done using a time base corrector - which  basically
captures  and re-creates  the signal.  But I could be wrong.

Yes, for devices that can't be synced, that is a solution. But for
multiple cameras, the preferred approach is to genlock them.

I had not understood you were trying to use the camera and not the
tape transport.

Was not aware that there are servo'd tape transports but I suppose
it's possible.

Also probably somewhat moot in the case of digital tape since the the
output signal has to be synthesized anyway; the tape just needs to
move at the speed to keep the read buffer between high and low
watermarks.