Up/Down Binary Counter with Dynamic Count-to Flag...

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[Beniamin Antal-Vaida]

Pe miercuri, 25 martie 2020, la 22:00:39 UTC+2, robee...@gmail.com a scris:

joi, 15 mai 2008, 14:40:44 UTC+3, SweetMusic a scris:
Hi,
I need to simulate this thing in Verilog vega.unitbv.ro/~nicula/asd/
hdl_lab/tema_pdf/DW03_bictr_dcnto.pdf

And here is my counter.v file

module counter(data, up_dn, cen, load, clk, count, tercnt, reset,
count_to);
parameter width=4;


input[width-1:0] data;
input[width-1:0] count_to;
input up_dn, cen, load, clk, reset;


output [width-1:0] count;
reg [width-1:0] count;
output tercnt;
reg tercnt;



always @(posedge clk or negedge reset)
if (~reset) begin
count<={width{4\'b0000}};
end
else begin
if(~load) begin
count<=data;
end
else begin
if (cen) begin
if (up_dn) begin
count<=count
+1;
if (count==count_to)
tercnt<=1;
end
else begin

count<=count-1;
if (count==count_to)
tercnt<=1;
end
end
end
end

always @(count or up_dn)

if (&count && up_dn)
tercnt <= 1;

else
if (~|count && !up_dn)
tercnt <= 1;

else
tercnt <= 0;


endmodule


****************************************************************************************************************

The problem is that when the count reaches to the count_to value(witch
is an input signal), tercn signal(terminate counting) dosent goes to
\"1\"

What do i do wrong?
thank you
Salut! Mai ai cumva aceasta tema salvata prin PC?

 

[Beniamin Antal-Vaida]

Pe miercuri, 25 martie 2020, la 22:00:39 UTC+2, robee...@gmail.com a scris:

joi, 15 mai 2008, 14:40:44 UTC+3, SweetMusic a scris:
Hi,
I need to simulate this thing in Verilog vega.unitbv.ro/~nicula/asd/
hdl_lab/tema_pdf/DW03_bictr_dcnto.pdf

And here is my counter.v file

module counter(data, up_dn, cen, load, clk, count, tercnt, reset,
count_to);
parameter width=4;


input[width-1:0] data;
input[width-1:0] count_to;
input up_dn, cen, load, clk, reset;


output [width-1:0] count;
reg [width-1:0] count;
output tercnt;
reg tercnt;



always @(posedge clk or negedge reset)
if (~reset) begin
count<={width{4\'b0000}};
end
else begin
if(~load) begin
count<=data;
end
else begin
if (cen) begin
if (up_dn) begin
count<=count
+1;
if (count==count_to)
tercnt<=1;
end
else begin

count<=count-1;
if (count==count_to)
tercnt<=1;
end
end
end
end

always @(count or up_dn)

if (&count && up_dn)
tercnt <= 1;

else
if (~|count && !up_dn)
tercnt <= 1;

else
tercnt <= 0;


endmodule


****************************************************************************************************************

The problem is that when the count reaches to the count_to value(witch
is an input signal), tercn signal(terminate counting) dosent goes to
\"1\"

What do i do wrong?
thank you
Salut! Mai ai cumva aceasta tema salvata prin PC?

Salut , ai facut cumva rost de aceasta tema ?