unused wires and VHDL architectures

[Neil Zanella]

Hello,

Upon synthesizing some VHDL code I get the following warning message from
the VHDL compiler (Xilinx Project Navigator). I know that this signal is
never used. Perhaps the VHDL code is wasting a wire in the implementation
so I should fix it. On the other hand, one wire might not make a big
difference for a really small design, so is there a way to suppress
the compiler warning message in this case? After all, the compiler
should be able to see that the wire is not being used and hence
leave it out of the bitfile that implemnts the given design.
Right?

WARNING:Xst:647 - Input <foo<4>> is never used.

Thanks,

Neil

 

[Peter Molesworth]

On Mon, 20 Oct 2003 19:12:02 -0230, Neil Zanella <nzanella@cs.mun.ca>
wrote:

Hello,

Upon synthesizing some VHDL code I get the following warning message from
the VHDL compiler (Xilinx Project Navigator). I know that this signal is
never used. Perhaps the VHDL code is wasting a wire in the implementation
so I should fix it. On the other hand, one wire might not make a big
difference for a really small design, so is there a way to suppress
the compiler warning message in this case? After all, the compiler
should be able to see that the wire is not being used and hence
leave it out of the bitfile that implemnts the given design.
Right?

WARNING:Xst:647 - Input <foo<4>> is never used.

Thanks,

Neil

Neil,

Don't worry about wasting any routing resources in your device. Any unused
inputs will be optimized out as you would find if you tried to assign a
pad type to them in the contraints editor or ucf file. Unfortunately I
don't think there is a way of turning this warning off in Xilinx Project
Navigator so you'll probably just have to live with it or remove unused IO
from you design.

Cheers,

Pete.

 

[Neil Zanella]

Thank you for your reply,

There was one component which I was reusing twice, once using all of the
outputs and another time using only half of them. Basically when you reuse
VHDL components you often don't want to use all of the inputs and outputs
available in that component. Al least not for quick-and-dirty designs.
Furthermore, in some board-level designs it may be the case that
purchasing several identical larger components that can perform
several functions is cheper than purchasing many more smaller
components that perform smaller tasks but are all different
from each other, because you may get bulk discounts by
purchasing larger but identical components.

For instance consider a VHDL design that makes use of a VHDL component
that implements the famous 74-series medium scale integration 74x157
multiplexer. This device has an active-low enable input (G) which
can be connected to the ground, two four-input vector

A = (4A, 3A, 2A, 1A)

and

B = (4B, 3B, 2B, 1B)

and an outut vector

Y = (4Y, 3Y, 2Y, 1Y)

The 74x157, being a MUX, also has a selection line, which consists of a
single signal, S, such that the output Y of the 74x157 is A when S = 0 and
the output Y is equal to B when S = 1.

So here we have a device that could be instantiated in such a way that the
S input is connected to ground and the B inputs are disconnected, since
they are not needed. Similarly, it could be that we are only interested
in half of the A values, say 1A and 2A, with 3A and 4A being disconnected.

Certainly in all of these cases diconnecting the wires is certainly not
useless and is what is meant: we want to use some component that we have
multiple copies of but don't need to use all of its wires.

So, it seems strange to me that VHDL would not have a construct such that
you could say something like the following (untested) code:

library ieee;
use ieee.std_logic_1164.all;

entity Foo is
port (
FoosS: in std_ulogic;
FoosA: in std_ulogic_vector(4 downto 1);
FoosY: out std_ulogic_vector(4 downto 1)
-- more stuff here
);
end entity Foo;

architecture arch of Foo is
component Mux74x157 is
port (
G: in std_ulogic;
S: in std_ulogic;
A: in std_ulogic_vector(4 downto 1);
B: in std_ulogic_vector(4 downto 1);
Y: out std_ulogic_vector(4 downto 1)
);
end component Mux74x157;
-- more stuff here
begin
U: Mux74x157
port map (
G => 0,
S => FoosS,
A => FoosA,
B => disconnected,
T => FoosY
);
end architecture arch;

library ieee;
use ieee.std_logic_1164.all;

entity Mux74x157 is
port (
G: in std_ulogic;
S: in std_ulogic;
A: in std_ulogic_vector(4 downto 1);
B: in std_ulogic_vector(4 downto 1);
Y: out std_ulogic_vector(4 downto 1)
);
end entity Mux74x157;

architecture arch of Mux74x157 is
begin
with S select
Y <=
A when '0',
B when '1',
"UUUU" when others;
end architecture arch;

On Wed, 22 Oct 2003, Peter Molesworth wrote:

Neil,

Don't worry about wasting any routing resources in your device. Any unused
inputs will be optimized out as you would find if you tried to assign a
pad type to them in the contraints editor or ucf file. Unfortunately I
don't think there is a way of turning this warning off in Xilinx Project
Navigator so you'll probably just have to live with it or remove unused IO
from you design.

Cheers,

Pete.

On Mon, 20 Oct 2003 19:12:02 -0230, Neil Zanella <nzanella@cs.mun.ca
wrote:

Upon synthesizing some VHDL code I get the following warning message from
the VHDL compiler (Xilinx Project Navigator). I know that this signal is
never used. Perhaps the VHDL code is wasting a wire in the implementation
so I should fix it. On the other hand, one wire might not make a big
difference for a really small design, so is there a way to suppress
the compiler warning message in this case? After all, the compiler
should be able to see that the wire is not being used and hence
leave it out of the bitfile that implemnts the given design.
Right?

WARNING:Xst:647 - Input <foo<4>> is never used.

 

[Peter Molesworth]

So, it seems strange to me that VHDL would not have a construct such that
you could say something like the following (untested) code:

library ieee;
use ieee.std_logic_1164.all;

entity Foo is
port (
FoosS: in std_ulogic;
FoosA: in std_ulogic_vector(4 downto 1);
FoosY: out std_ulogic_vector(4 downto 1)
-- more stuff here
);
end entity Foo;

architecture arch of Foo is
component Mux74x157 is
port (
G: in std_ulogic;
S: in std_ulogic;
A: in std_ulogic_vector(4 downto 1);
B: in std_ulogic_vector(4 downto 1);
Y: out std_ulogic_vector(4 downto 1)
);
end component Mux74x157;
-- more stuff here
begin
U: Mux74x157
port map (
G => 0,
S => FoosS,
A => FoosA,
B => disconnected,
T => FoosY
);
end architecture arch;

You could just create a signal to attach to the unused inputs and assign
to this signal a default value. The synthesis/place&route tools will still
optimize out the unused logic but won't complain about unused inputs. For
example:

architecture arch of Foo is
-- declarations here
signal FoosB : std_logic_vector (4 downto 1) := (others => '0');
signal Gnd : std_logic := '0';

begin

U1 : Mux74x157
port map (
G => FoosG,
S => Gnd,
A => FoosA,
B => FoosB, -- Unused inputs assigned to "0000"
Y => FoosY
);

end arch;

Similarly for unused outputs VHDL provides the ability to specify the
ports as 'open' in the component instantiation. For example:

U1 : DFF
port map (
Clk => ClkIn,
Clr => Clear,
D => DataIn,
Q => DataOut,
nQ => open -- nothing gets attached here
);

Note that this only works for whole ports and not parts of ports so if in
your code above you wanted to only use 2 bits of Y then you would still
have to assign all 4 bits to a signal as open could not be used.

Cheers,

Pete.

 

[Neil Zanella]

Peter Molesworth <noemail@anonymous.net> wrote in message

You could just create a signal to attach to the unused inputs and assign
to this signal a default value. The synthesis/place&route tools will still
optimize out the unused logic but won't complain about unused inputs.
For example:

architecture arch of Foo is
-- declarations here
signal FoosB : std_logic_vector (4 downto 1) := (others => '0');
signal Gnd : std_logic := '0';

begin

U1 : Mux74x157
port map (
G => FoosG,
S => Gnd,
A => FoosA,
B => FoosB, -- Unused inputs assigned to "0000"
Y => FoosY
);

end arch;

This works but is somewhat misleading. Someone reading the design could be
erroneously misled into thinking that the signals FoosB and Gnd are
actually used for something when in fact they don't serve any particular
purpose other than bypassing the compiler warnings.

Similarly for unused outputs VHDL provides the ability to specify the
ports as 'open' in the component instantiation. For example:

U1 : DFF
port map (
Clk => ClkIn,
Clr => Clear,
D => DataIn,
Q => DataOut,
nQ => open -- nothing gets attached here
);

I wonder whether this works for inputs too. After all, there could be
inputs that under certain combinations of other inputs play no role in
determining the outputs. In this case it seems the design would be better
documented if the keyword open was used for such inputs as well. As I
understand it the open keyword may also be used for inputs as well so long
as default values are provided for the inputs in the port part of the
entity declaration.

Note that this only works for whole ports and not parts of ports so if
in your code above you wanted to only use 2 bits of Y then you would still
have to assign all 4 bits to a signal as open could not be used.

The problem is that when the four bit signal is connected to another
component X and that component X does not use all four bits the compiler
complains. So there is no elegant way to get rid of that warning just
because I am using an std_ulogic_vector instead of four std_ulogic
signals?

Thanks,

Neil

 

[David R Brooks]

Comments below...

Neil Zanella <nzanella@cs.mun.ca> wrote:

:
eter Molesworth <noemail@anonymous.net> wrote in message
:
:> You could just create a signal to attach to the unused inputs and assign
:> to this signal a default value. The synthesis/place&route tools will still
:> optimize out the unused logic but won't complain about unused inputs.
:> For example:
:>
:> architecture arch of Foo is
:> -- declarations here
:> signal FoosB : std_logic_vector (4 downto 1) := (others => '0');
:> signal Gnd : std_logic := '0';
:>
:> begin
:>
:> U1 : Mux74x157
:> port map (
:> G => FoosG,
:> S => Gnd,
:> A => FoosA,
:> B => FoosB, -- Unused inputs assigned to "0000"
:> Y => FoosY
:> );
:>
:> end arch;
:
:This works but is somewhat misleading. Someone reading the design could be
:erroneously misled into thinking that the signals FoosB and Gnd are
:actually used for something when in fact they don't serve any particular
urpose other than bypassing the compiler warnings.

Just use a more meaningful dummy signal name, eg "unused_inputs".
:
:> Similarly for unused outputs VHDL provides the ability to specify the
:> ports as 'open' in the component instantiation. For example:
:>
:> U1 : DFF
:> port map (
:> Clk => ClkIn,
:> Clr => Clear,
:> D => DataIn,
:> Q => DataOut,
:> nQ => open -- nothing gets attached here
:> );
:
:I wonder whether this works for inputs too. After all, there could be
:inputs that under certain combinations of other inputs play no role in
:determining the outputs. In this case it seems the design would be better
:documented if the keyword open was used for such inputs as well. As I
:understand it the open keyword may also be used for inputs as well so long
:as default values are provided for the inputs in the port part of the
:entity declaration.
:
You can't have "open" inputs, because floating inputs in logic are a
Bad Thing. In practice, you would always tie those unused inputs to
something: VHDL just requires you tell it so.

:> Note that this only works for whole ports and not parts of ports so if
:> in your code above you wanted to only use 2 bits of Y then you would still
:> have to assign all 4 bits to a signal as open could not be used.
:
:The problem is that when the four bit signal is connected to another
:component X and that component X does not use all four bits the compiler
:complains. So there is no elegant way to get rid of that warning just
:because I am using an std_ulogic_vector instead of four std_ulogic
:signals?
:
But you can still connect the full-width vector to a named signal,
then rip the bits you need from that signal as inputs to another
component. Again, think hardware. That 4-bit vector is a 4-pin output
socket: you choose to wire only 3 of the pins. That's what you say in
VHDL. The full-width signal effectively names the plug that goes in
that socket (must be 4-pin, to mate with it): then you rip the lines
you actually use.