Unused signals in Modelsim

[ALuPin]

Hi newsgroup users,

maybe you can help me on the following question:

Does Modelsim remove registered signals which are unused or not
connected to output pins?
Is there a possibility to avoid this without using output pins?

Kind regards

 

[Tim Hubberstey]

ALuPin wrote:

Hi newsgroup users,

maybe you can help me on the following question:

Does Modelsim remove registered signals which are unused or not
connected to output pins?
Is there a possibility to avoid this without using output pins?

ModelSim is a simulator and does not remove *anything*. Whatever you
declare is in there, whether it has any drivers attached or not.

Your question really only has relevance when applied to a synthesizer.
And, yes, any decent synthesizer will strip out all logic, registered or
combinational, that does not affect one or more outputs. There may be a
synthesis switch to defeat this behavior but it will depend on the
synthesizer.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[ALuPin]

Hi,

but why are the signals which are not used or connected to output pins
undefined when simulating?
When I connect them to output pins they are not!



Tim Hubberstey <bogus@bogusname.com> wrote in message news:<94TBc.6792$mm3.803@clgrps13>...

ALuPin wrote:

Hi newsgroup users,

maybe you can help me on the following question:

Does Modelsim remove registered signals which are unused or not
connected to output pins?
Is there a possibility to avoid this without using output pins?

ModelSim is a simulator and does not remove *anything*. Whatever you
declare is in there, whether it has any drivers attached or not.

Your question really only has relevance when applied to a synthesizer.
And, yes, any decent synthesizer will strip out all logic, registered or
combinational, that does not affect one or more outputs. There may be a
synthesis switch to defeat this behavior but it will depend on the
synthesizer.

 

[Tim Hubberstey]

ALuPin wrote:

but why are the signals which are not used or connected to output pins
undefined when simulating?

First, we need to clarify something: VHDL does not have "pins", it has
"ports". "Pins" are a physical feature of real parts and as such only
have meaning to a synthesizer. I'm going to assume you mean ports when
you say pins. I'm also going to assume you are talking about
std_(u)logic signals and vectors.

All std_(u)logic type signals (and variables) are assigned the value 'U'
at time=0. If nothing drives the signal, this value never changes.
Signals not connected to output ports but driven by something in the
code will have values appropriate to the attached driver(s) as defined
by the resolution function. It is important to be aware of the
distinction between the values of 'U' and 'X'. 'X' does not mean
"undefined", it means "unknown". A common cause of 'X' is
unintentionally having 2 or more drivers attached to a signal and
driving conflicting values.

When I connect them to output pins they are not!

I'm sorry but I don't believe this. A port of type "out" or "buffer"
serves only to make the value of an internal signal available outside an
architecture. It cannot influence the value assigned to the signal
driving it inside the architecture. Ports of type "inout" or "in" are
the only ports that can affect internal values.

Furthermore, 'X' always "wins", except against 'U', (see the std_logic
resolution function) so you can't attach any driver to a signal that
will make an 'X' go away. In other words, there is nothing that you can
drive through a port that will change an 'X' to something else.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com