unused signal

[titi]

When I use a component, is it recommended to connect each signal?
Is it possible to use the same component, without creating the "unused"
signal?

for example:

entity my_component is
port(some_input : in std_logic;
some_output : out std_logic_vector(3 downto 0));
end my_component;

....

signal unused : std_logic_vector(1 downto 0);
signal data : std_logic_vector(1 downto 0);
signal i : std_logic;

....

my_component : my_component
port map (
some_input => i,
some_output(0)=>data(0),
some_output(1)=>data(1),
some_output(2)=>unused(0),
some_output(3)=>unused(1)
);

 

[titi]

titi a écrit :

When I use a component, is it recommended to connect each signal?
Is it possible to use the same component, without creating the "unused"
signal?

for example:

entity my_component is
port(some_input : in std_logic;
some_output : out std_logic_vector(3 downto 0));
end my_component;

...

signal unused : std_logic_vector(1 downto 0);
signal data : std_logic_vector(1 downto 0);
signal i : std_logic;

...

my_component : my_component
port map (
some_input => i,
some_output(0)=>data(0),
some_output(1)=>data(1),
some_output(2)=>unused(0),
some_output(3)=>unused(1)
);

It looks like it is possible to use the open keyword.

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=4407&BV_SessionID=@@@@1659239848.1173452183@@@@&BV_EngineID=ccchaddkfdmfdhgcefeceihdffhdfjf.0

For exemple:

my_component : my_component
port map (
some_input => i,
some_output(0)=>data(0),
some_output(1)=>data(1),
some_output(2)=>open,
some_output(3)=>open
);

 

[weber]

On 9 mar, 12:00, titi <t...@nospam.fr> wrote:

titi a écrit :



When I use a component, is it recommended to connect each signal?
Is it possible to use the same component, without creating the "unused"
signal?

for example:

entity my_component is
port(some_input : in std_logic;
some_output : out std_logic_vector(3 downto 0));
end my_component;

...

signal unused : std_logic_vector(1 downto 0);
signal data : std_logic_vector(1 downto 0);
signal i : std_logic;

...

my_component : my_component
port map (
some_input => i,
some_output(0)=>data(0),
some_output(1)=>data(1),
some_output(2)=>unused(0),
some_output(3)=>unused(1)
);

It looks like it is possible to use the open keyword.

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPageP...

For exemple:

my_component : my_component
port map (
some_input => i,
some_output(0)=>data(0),
some_output(1)=>data(1),
some_output(2)=>open,
some_output(3)=>open
);

Anf if it's an input you can connect on 0
some_input => '0',

 

[Alan Peter Fitch]

titi wrote:

titi a écrit :

It looks like it is possible to use the open keyword.

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=4407&BV_SessionID=@@@@1659239848.1173452183@@@@&BV_EngineID=ccchaddkfdmfdhgcefeceihdffhdfjf.0


For exemple:

my_component : my_component
port map (
some_input => i,
some_output(0)=>data(0),
some_output(1)=>data(1),
some_output(2)=>open,
some_output(3)=>open
);

Hi,
in VHDL 87 what you describe will work. In VHDL 93 onwards, it is not
allowed - either the whole vector must be open (disconnected) or all
elements must be connected,
regards
Alan

Doulos

--
Alan Fitch
(to get my address, remove '_'s, substitute 'lastname', fix 'at')