ununderstandable compilation error

M

marc

Guest
Hello all,
i am fairly new to the verilog syntax and concepts
and so the following code may seem inapropriate

however, i am trying to build a cla with a module within a module
approach
i receive the following errors over the assign lines can someone
wxplain my wrondoings?


** Error: D:/This_is_my_Hard_disk/year3/Summer/Techen/Tl_examp/four_bit_cla.v(22):
LHS in force may not be a net: g_one_zero
** Error: D:/This_is_my_Hard_disk/year3/Summer/Techen/Tl_examp/four_bit_cla.v(23):
LHS in force may not be a net: p_one_zero


module two_bit_cla(g_one_zero,p_one_zero,s_2bit,x_2bit,y_2bit,cin);
input [1:0] x_2bit,y_2bit;
input cin;
output [1:0]s_2bit;
reg Dont_care;
reg [1:0]gen,prop;
reg c1;
output g_one_zero,p_one_zero;

adder s0(Dont_care,s_2bit[0],x_2bit[0],y_2bit[0],cin); //using 1-bit
adder
generate_prop gp0(x_2bit[0],y_2bit[0],gen[0],prop[0]);

adder s1(Dont_care,s_2bit[1],x_2bit[1],y_2bit[1],c1); //using 1-bit
adder
generate_prop gp1(x_2bit[1],y_2bit[1],gen[1],prop[1]);

always @(x_2bit or y_2bit or cin)
begin
c1 = gen[0] || (prop[0] && cin);
//c2 = gen[1] || (prop[1] && gen[0]) || (prop[1] && prop[0] && cin);
//c3 = gen[2] || (prop[2]&& gen[1]) || (prop[2] && prop[1] && gen[0])
//||(prop[2]&& prop[1] && prop[0]&&cin);
assign g_one_zero = gen[1] || (prop[1] && gen[0]);
assign p_one_zero = prop[1] && prop [0];
end
endmodule

module generate_prop(x,y,gen,prop);
input x,y;
output gen,prop;
always@(x or y)
begin
end
assign gen = x && y;
assign prop = x ^ y;
endmodule

module adder ( cout, sum, a, b, cin ) ;

parameter n = 0 ;

output cout ;
output [n:0] sum ;

input [n:0] a, b ;
input cin ;

assign { cout, sum } = a + b + cin ;

endmodule


i try to use instances of models in one larger model as my idea is
to recursivly use 2bit cla for a 4bit cla and so on.

Thanks in advance,
marc.
 
marc wrote:
Hello all,
i am fairly new to the verilog syntax and concepts
and so the following code may seem inapropriate

however, i am trying to build a cla with a module within a module
approach
i receive the following errors over the assign lines can someone
wxplain my wrondoings?


** Error: D:/This_is_my_Hard_disk/year3/Summer/Techen/Tl_examp/four_bit_cla.v(22):
LHS in force may not be a net: g_one_zero
** Error: D:/This_is_my_Hard_disk/year3/Summer/Techen/Tl_examp/four_bit_cla.v(23):
LHS in force may not be a net: p_one_zero


module two_bit_cla(g_one_zero,p_one_zero,s_2bit,x_2bit,y_2bit,cin);
input [1:0] x_2bit,y_2bit;
input cin;
output [1:0]s_2bit;
reg Dont_care;
reg [1:0]gen,prop;
reg c1;
output g_one_zero,p_one_zero;

adder s0(Dont_care,s_2bit[0],x_2bit[0],y_2bit[0],cin); //using 1-bit
adder
generate_prop gp0(x_2bit[0],y_2bit[0],gen[0],prop[0]);

adder s1(Dont_care,s_2bit[1],x_2bit[1],y_2bit[1],c1); //using 1-bit
adder
generate_prop gp1(x_2bit[1],y_2bit[1],gen[1],prop[1]);

always @(x_2bit or y_2bit or cin)
begin
c1 = gen[0] || (prop[0] && cin);
//c2 = gen[1] || (prop[1] && gen[0]) || (prop[1] && prop[0] && cin);
//c3 = gen[2] || (prop[2]&& gen[1]) || (prop[2] && prop[1] && gen[0])
//||(prop[2]&& prop[1] && prop[0]&&cin);
assign g_one_zero = gen[1] || (prop[1] && gen[0]);
assign p_one_zero = prop[1] && prop [0];
Continuous assignments should be placed outside of always blocks.
Click to expand...
You did not user x_2bit or y_2bit within this block, why put them in the
sensitivity list?
end
endmodule

module generate_prop(x,y,gen,prop);
input x,y;
output gen,prop;
always@(x or y)
begin
end
assign gen = x && y;
x & y
assign prop = x ^ y;
endmodule

module adder ( cout, sum, a, b, cin ) ;

parameter n = 0 ;

output cout ;
output [n:0] sum ;

input [n:0] a, b ;
input cin ;

assign { cout, sum } = a + b + cin ;

endmodule


i try to use instances of models in one larger model as my idea is
to recursivly use 2bit cla for a 4bit cla and so on.

Thanks in advance,
marc.
Click to expand...
 
Correcto mundo!!!

Thank you very much indeed.

Jason Zheng <jzheng@jpl.nasa.gov> wrote in message news:<cgje84$pp$1@nntp1.jpl.nasa.gov>...
marc wrote:
Hello all,
i am fairly new to the verilog syntax and concepts
and so the following code may seem inapropriate

however, i am trying to build a cla with a module within a module
approach
i receive the following errors over the assign lines can someone
wxplain my wrondoings?


** Error: D:/This_is_my_Hard_disk/year3/Summer/Techen/Tl_examp/four_bit_cla.v(22):
LHS in force may not be a net: g_one_zero
** Error: D:/This_is_my_Hard_disk/year3/Summer/Techen/Tl_examp/four_bit_cla.v(23):
LHS in force may not be a net: p_one_zero


module two_bit_cla(g_one_zero,p_one_zero,s_2bit,x_2bit,y_2bit,cin);
input [1:0] x_2bit,y_2bit;
input cin;
output [1:0]s_2bit;
reg Dont_care;
reg [1:0]gen,prop;
reg c1;
output g_one_zero,p_one_zero;

adder s0(Dont_care,s_2bit[0],x_2bit[0],y_2bit[0],cin); //using 1-bit
adder
generate_prop gp0(x_2bit[0],y_2bit[0],gen[0],prop[0]);

adder s1(Dont_care,s_2bit[1],x_2bit[1],y_2bit[1],c1); //using 1-bit
adder
generate_prop gp1(x_2bit[1],y_2bit[1],gen[1],prop[1]);

always @(x_2bit or y_2bit or cin)
begin
c1 = gen[0] || (prop[0] && cin);
//c2 = gen[1] || (prop[1] && gen[0]) || (prop[1] && prop[0] && cin);
//c3 = gen[2] || (prop[2]&& gen[1]) || (prop[2] && prop[1] && gen[0])
//||(prop[2]&& prop[1] && prop[0]&&cin);
assign g_one_zero = gen[1] || (prop[1] && gen[0]);
assign p_one_zero = prop[1] && prop [0];
Continuous assignments should be placed outside of always blocks.
You did not user x_2bit or y_2bit within this block, why put them in the
sensitivity list?
end
endmodule

module generate_prop(x,y,gen,prop);
input x,y;
output gen,prop;
always@(x or y)
begin
end
assign gen = x && y;
x & y
assign prop = x ^ y;
endmodule

module adder ( cout, sum, a, b, cin ) ;

parameter n = 0 ;

output cout ;
output [n:0] sum ;

input [n:0] a, b ;
input cin ;

assign { cout, sum } = a + b + cin ;

endmodule


i try to use instances of models in one larger model as my idea is
to recursivly use 2bit cla for a 4bit cla and so on.

Thanks in advance,
marc.
Click to expand...
 
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