Until Looping Construct

[Gokul]

Hi all,

I have a Variable [Register] named var.
var is a 6-bit Register.So it can hold 0 to 63.
var is assigned as follows: var = {$random}

Now, I wanted the value in var to be even always.
var should be 0,2,4 ... 62.
Only if the var holds a even value, I should enter the loop.Or else I
should try for the next value using $random function.

Precisely, I wanted the following functionality.

until (var % 2 ) == 0;
var = {$random}

if (var %2 == 0)
begin
Loop begins
end

Is there any precise way to do this in Verilog ???

 

[Gokul]

I do understand that the following will work.

if ((var = {$random}) % 2 == 0)
begin
Loop begins
end

But I am on the look for a more elegant way of doing this.

Is there anything ???

 

[Marcus Harnisch]

Gokul <gokul.bits@gmail.com> writes:

I do understand that the following will work.

if ((var = {$random}) % 2 == 0)
begin
Loop begins
end

But I am on the look for a more elegant way of doing this.

Is there anything ???

Shift a zero bit into your random value. `var' is still as random as
before.

,----
| var = $random << 1;
|
| // Loop begins
`----

Regards
Marcus

--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

(seen on http://www.veripool.com/verilog-mode_news.html)

 

[Gokul]

Thanks Marcus.

It really Helped.