Unsupported verilog construct with synopsys DC?

F

Fazela

Guest
Hi All,
I have a verilog design which uses the following construct:

typedef enum {INVALID, SHARED, EXCLUSIVE} Block_status;

When I try to synthesize this design using Synopsys Design Compiler,
it complains saying that:

Syntax error at or near token 'typedef'. (VER-294)

I was just wondering if this construct is unsupported by DC or what?
because this is like a benchmark design which I downloaded and so I
dont
understand how this would be a syntax error.

Thanks,
Fazela
 
Fazela wrote:
Hi All,
I have a verilog design which uses the following construct:

typedef enum {INVALID, SHARED, EXCLUSIVE} Block_status;

When I try to synthesize this design using Synopsys Design Compiler,
it complains saying that:

Syntax error at or near token 'typedef'. (VER-294)

I was just wondering if this construct is unsupported by DC or what?
because this is like a benchmark design which I downloaded and so I
dont
understand how this would be a syntax error.

Thanks,
Fazela
Click to expand...
I didn't readily find "supported Verilog Constructs" on the product
pages (I don't use the tool). Do you know if your version of DC
supports System Verilog or Verilog2005? The typedef is new since
Verilog2001.
 
Hi John,
My DC version is:
Version X-2005.09 for linux -- Mar 02, 2006.
I am not sure what verilog it supports.

Thanks,
Fazela

But it is still not supporting.

John_H wrote:
Fazela wrote:
Hi All,
I have a verilog design which uses the following construct:

typedef enum {INVALID, SHARED, EXCLUSIVE} Block_status;

When I try to synthesize this design using Synopsys Design Compiler,
it complains saying that:

Syntax error at or near token 'typedef'. (VER-294)

I was just wondering if this construct is unsupported by DC or what?
because this is like a benchmark design which I downloaded and so I
dont
understand how this would be a syntax error.

Thanks,
Fazela

I didn't readily find "supported Verilog Constructs" on the product
pages (I don't use the tool). Do you know if your version of DC
supports System Verilog or Verilog2005? The typedef is new since
Verilog2001.
Click to expand...
 
On 14 Jun 2006 19:50:29 -0700, "Fazela" <fazela@gmail.com> wrote:

Hi John,
My DC version is:
Version X-2005.09 for linux -- Mar 02, 2006.
I am not sure what verilog it supports.
Click to expand...
Speak to your friendly Synopysys apps person. SystemVerilog
features are available under a separate licence.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Thu, 15 Jun 2006 09:04:17 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

My DC version is:
Version X-2005.09 for linux -- Mar 02, 2006.
I am not sure what verilog it supports.

Speak to your friendly Synopysys apps person. SystemVerilog
features are available under a separate licence.
Click to expand...
Sorry, I forgot to mention: When doing the [read] or [analyze]
command to read your SystemVerilog source code, you need
to add the option
-format sverilog

At that point, if you don't have the licence feature installed,
DC will tell you about it.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hi Jonathan,
Thanks a lot, I am new to verilog and I didnt figure out that this was
system verilog. Now it works.

Thanks,
Fazela
Jonathan Bromley wrote:
On Thu, 15 Jun 2006 09:04:17 +0100, Jonathan Bromley
jonathan.bromley@MYCOMPANY.com> wrote:

My DC version is:
Version X-2005.09 for linux -- Mar 02, 2006.
I am not sure what verilog it supports.

Speak to your friendly Synopysys apps person. SystemVerilog
features are available under a separate licence.

Sorry, I forgot to mention: When doing the [read] or [analyze]
command to read your SystemVerilog source code, you need
to add the option
-format sverilog

At that point, if you don't have the licence feature installed,
DC will tell you about it.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
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