Unsupported verilog construct with synopsys DC?

[Fazela]

Hi All,
I have a verilog design which uses the following construct:

typedef enum {INVALID, SHARED, EXCLUSIVE} Block_status;

When I try to synthesize this design using Synopsys Design Compiler,
it complains saying that:

Syntax error at or near token 'typedef'. (VER-294)

I was just wondering if this construct is unsupported by DC or what?
because this is like a benchmark design which I downloaded and so I
dont
understand how this would be a syntax error.

Thanks,
Fazela

 

[michaelst@gmail.com]

Because Synopsys does not support SystemVerilog yet?
Synthesis of SystemVerilog requires special license. I believe you
don't have it.

Fazela wrote:

Hi All,
I have a verilog design which uses the following construct:

typedef enum {INVALID, SHARED, EXCLUSIVE} Block_status;

When I try to synthesize this design using Synopsys Design Compiler,
it complains saying that:

Syntax error at or near token 'typedef'. (VER-294)

I was just wondering if this construct is unsupported by DC or what?
because this is like a benchmark design which I downloaded and so I
dont
understand how this would be a syntax error.

Thanks,
Fazela