Unsigned 8 bit adder with carry in and out example

[Travis]

I got this example from
http://asic.co.in/Index_files/verilogexamples.htm#link37

Quote follows:
"Following is the Verilog code for an unsigned 8-bit adder with carry in and carry out.
module adder(a, b, ci, sum, co);
input ci;
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output co;
wire [8:0] tmp;

assign tmp = a + b + ci;
assign sum = tmp [7:0];
assign co = tmp [8];

endmodule
"

I see that tmp is assigned as a wire. Wouldn't tmp have to be a register, as it is storing a value? Also, wouldn't output have to be an output reg, if it is storing this value?

It looks like something that'd be fine for simulation, but wouldn't work correctly for synthesis.

Thanks all!

 

[Kevin Neilson]

A cooler way to write this is to eliminate tmp and just do:

assign {co, sum} = a + b + ci;


Since there is no clock, this is combinatorial, so the normal way to write this would be with wires. This will synthesize. Nothing is "stored" because there are no flip-flops. I believe with SystemVerilog you can call the outputs regs and still use "assign". Alternatively, you can use registers and an always block:

....
output reg [7:0] sum;
output reg co;
....
always@*
{co,sum} = a+b+ci;

The syntax is different, but it's still combinatorial logic, and the "regs" don't synthesize into flops.

 

[Travis]

Thank you for both the cooler method, and the synthesis tip.

On Friday, July 12, 2013 1:02:56 PM UTC-7, Kevin Neilson wrote:

A cooler way to write this is to eliminate tmp and just do:



assign {co, sum} = a + b + ci;





Since there is no clock, this is combinatorial, so the normal way to write this would be with wires. This will synthesize. Nothing is "stored" because there are no flip-flops. I believe with SystemVerilog you can call the outputs regs and still use "assign". Alternatively, you can use registers and an always block:



...

output reg [7:0] sum;

output reg co;

...

always@*

{co,sum} = a+b+ci;



The syntax is different, but it's still combinatorial logic, and the "regs" don't synthesize into flops.