Unknown condition in if statement is treated in what manner

Hi everyone,
I have run this small code and seeing many variations can you plaese
suggest why is that so:

module top;

reg [1:0] c;
reg [1:0] a = 2'b10;
reg [1:0] b = 2'b01;
reg [1:0] if_out;
wire [1:0] out;

assign out = c ? a : b;

initial
begin
#1 c = 2'b1x;
if(c)
if_out = a;
else
if_out = b;
#1 $display("out:%b, if_out:%b, c:%b",out,if_out,c);
end
endmodule

output:
out:10, if_out:10, c:1x

Now if i change c to 2'bXX

out:xx, if_out:01, c:xx

Now if i change c to 2'bx0

out:xx, if_out:01, c:x0

 

[Jonathan Bromley]

On Wed, 5 Nov 2008 23:25:36 -0800 (PST), gtalk.nikhil@gmail.com wrote:

Hi everyone,
I have run this small code and seeing many variations can you plaese
suggest why is that so:

Interesting, but your example makes things a little too
complicated for easy explanation..... let's try.

You are using the 2-bit register 'c' as a test
condition in two places:

assign out = c ? a : b;

if(c)

In both cases the meaning is clear, and in
both cases it is the same:

TRUE if c is definitely non-zero (has at least one 1 bit)
FALSE if c is exactly zero
UNKNOWN if c contains any X/Z bits and no 1 bits

You can get exactly this result by looking at the
reduction-OR operator |c which gives 1'b1, 1'b0, 1'bX
for those three cases.

OK, now we know how a truth-value is handled in Verilog,
let's see what happens to it in those two statements.
We'll do procedural if() first, because it's easier:

if (Condition)
TRUE_branch;
else
FALSE_branch;

It's easy to understand this if Condition is TRUE or
FALSE, but what happens if Condition is UNKNOWN?
There is no third branch for "don't know"! So Verilog
must make a choice; that choice is to do the FALSE branch
if Condition is unknown. (That's guaranteed by the LRM.)
This completely explains your results on "if_out".

Now let's look at the more tricky case:

assign out = c ? a: b;

In this case Verilog can be rather more clever in the way
it handles unknowns. Obviously if c is TRUE you get out=a,
and if c is FALSE you get out=b. But if c is UNKNOWN,
Verilog looks at EACH BIT POSITION of a, b independently.
In a given bit position, if the corresponding bits in a
and b are the same then we assign that value to the
corresponding bit of out!

Here's the reasoning:
* c?a:b models a multiplexer. c is the select input.
* If the select input is unknown, but the two data
inputs are identical, then the output is sure to
be the same as the data inputs.
* If the select input is unknown but the two data
inputs are different, then we can't predict the
outcome; so we drive X on to the output.

Try this example:

reg [3:0] d0, d1, y;
initial begin
d0 = 'b1100;
d1 = 'b0101;
y = 1'bx ? d0: d1;
$display("d0 = %b", d0);
$display("d1 = %b", d1);
$display(" y = %b", y);
end

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

On Nov 6, 2:21 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Wed, 5 Nov 2008 23:25:36 -0800 (PST), gtalk.nik...@gmail.com wrote:
Hi everyone,
I have run this small code and seeing many variations can you plaese
suggest why is that so:

Interesting, but your example makes things a little too
complicated for easy explanation..... let's try.

You are using the 2-bit register 'c' as a test
condition in two places:

assign out = c ? a : b;
if(c)

In both cases the meaning is clear, and in
both cases it is the same:

TRUE if c is definitely non-zero (has at least one 1 bit)
FALSE if c is exactly zero
UNKNOWN if c contains any X/Z bits and no 1 bits

You can get exactly this result by looking at the
reduction-OR operator |c which gives 1'b1, 1'b0, 1'bX
for those three cases.

OK, now we know how a truth-value is handled in Verilog,
let's see what happens to it in those two statements.
We'll do procedural if() first, because it's easier:

if (Condition)
TRUE_branch;
else
FALSE_branch;

It's easy to understand this if Condition is TRUE or
FALSE, but what happens if Condition is UNKNOWN?
There is no third branch for "don't know"! So Verilog
must make a choice; that choice is to do the FALSE branch
if Condition is unknown. (That's guaranteed by the LRM.)
This completely explains your results on "if_out".

Now let's look at the more tricky case:

assign out = c ? a: b;

In this case Verilog can be rather more clever in the way
it handles unknowns. Obviously if c is TRUE you get out=a,
and if c is FALSE you get out=b. But if c is UNKNOWN,
Verilog looks at EACH BIT POSITION of a, b independently.
In a given bit position, if the corresponding bits in a
and b are the same then we assign that value to the
corresponding bit of out!

Here's the reasoning:
* c?a:b models a multiplexer. c is the select input.
* If the select input is unknown, but the two data
inputs are identical, then the output is sure to
be the same as the data inputs.
* If the select input is unknown but the two data
inputs are different, then we can't predict the
outcome; so we drive X on to the output.

Try this example:

reg [3:0] d0, d1, y;
initial begin
d0 = 'b1100;
d1 = 'b0101;
y = 1'bx ? d0: d1;
$display("d0 = %b", d0);
$display("d1 = %b", d1);
$display(" y = %b", y);
end

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Hi,
Great explanation thanks a lot for your time

 

can you please share the page number or context which says .. in unknown case if(exp)
....if exp is unknown .. else will be executed

 

[unfrostedpoptart]

On Thursday, April 2, 2020 at 7:49:42 AM UTC-7, vishal...@gmail.com wrote:

can you please share the page number or context which says .. in unknown case if(exp)
...if exp is unknown .. else will be executed

Why are you responding to a 12-year-old post?