Unknown bug in program

[Leow Yuan Yeow]

Hi, I have a strange problem in the attached program iir-3t.vhd, which I
am unable to figure out. The problem is that a particular 32-bit integer
register is assigned a constant value of 1 for post-place-and-route
simulation and also on my RC100 board(stuck in infinite loop with no
output because of it). However, the register output correctly in
behavioral simulation. The code snippet having the error is:

when T2_S19 =>
TMP_T59 <= 3 * R0_F0_incr(THREAD_NUM);
T2_STATE <= T2_S20;

when T2_S20 =>
TMP_T60 <= k_priv(THREAD_NUM) + TMP_T59;
T2_STATE <= T2_S21;

when T2_S21 =>
k_priv(THREAD_NUM) <= TMP_T60;
T2_STATE <= T2_S9;

In the PPAR simulation, TMP_T59 has a constant value of 3, which is
correct. However, the value of TMP_T60 and k_priv(THREAD_NUM)
(THREAD_NUM is a constant in each process) which are integers, have its
value stuck at 1 even though the same code is executed past many times.
TMP_60 is never assigned anywhere else, and this problem does not occur
in simulation (i.e. the value of TMP_60 and k_priv actually gets
incremented).

Any help to see where the problem lies is deeply appreciated!

 

[Mike Treseler]

Leow Yuan Yeow wrote:

The problem is that a particular 32-bit integer
register is assigned a constant value of 1 for post-place-and-route
simulation and also on my RC100 board(stuck in infinite loop with no
output because of it). However, the register output correctly in
behavioral simulation.

I would suspect a synchronization or Fmax problem.
Did static timing pass?

Any help to see where the problem lies is deeply appreciated!

I will presume you actually
compiled your package before main
rather than the order shown in your code.

This code is an good example of the fact
that a state machine is not the
optimum description style for
a large shift register.

-- Mike Treseler