Unity gain buffer amplifier to lower impedance

[abhijit]

Greetings!

I have a medium frequency analog signal coming from
a DAC (AD557), but the DAC's output impedance is
too high for my purpose.

So I am trying to design a medium frequency unity gain
buffer amplifier with flat bandwidth from 10Hz to 2MHz,
but I have the following restrictions:

- single 5V supply (split power supply cannot be used)

- input voltage (coming from the DAC) is in the range
0 - 2.6V (it really goes down to 0V)

- so buffer must be able to handle (without distortion)
input voltages really down to 0 volts

- input impedance should be > 50k, preferably fet-input
so that it can be ac-coupled with a 0.1uF cap

- output impedance must be less than 50 ohms

- must have very low distortion

- preferably no large caps

- op-amp is OK provided it is +5V single-supply,
low distortion, and has common-mode input
really going down to negative-rail (ground)

I have designed the circuit below, which gives
a THD of about 0.3% with a 50 ohm load impedance.
Also it may not be very good driving capacitive
loads such as cables. So I am looking for something
with lower distortion and lower output impedance
which can drive capacitive loads with the above
restrictions.

Anyone with more ideas?

Abhijit Dasgupta

============================
Spice file (Berkeley spice3)
============================

Buffer with ac-coupled input to njfet, bipolar output
*
* Improving distortion with a current sink feeding
* the emitter of q1
*
* With rload = 1.5k, THD is minimal (< 0.001%) for
* 0-3V p-p input, but THD increases under load,
* to almost 0.3% when rload = 50 ohms
*
* 3 +--------+-------o vcc +5V
* | |
* |-+ j1 |
* 1 cin 2 | J310 |
* vin o---||---+--->|-+ |
* 0.1uF | | 4 |/ q1
* < +------| 2N2222A
* rgate < | |\.e
* 4.7Meg < < |
* | < rsrc +---o<-----+ vout
* | < 47K | 5 |
* | | | |
* | +--------+ |
* | | |
* 3 | rb 6 |/ q2 |
* vcc -----------/\/\/\-+---| 2N2222A |
* | 2.2K | |\.e |
* | _|_ | |
* | d1 \./ + 7 < external
* | 1N914 -+- | < rload
* | | < < 50 ohms
* | +8 < re |
* | _|_ < 56 ohms |
* | d2 \./ | |
* | 1N914 -+- | |
* | | | |
* 0 +---------+-----+---o<-----+ GND
*
vcc 3 0 dc 5
vin 1 0 dc 0 ac sin(1.5 1.5 1000)
cin 1 2 0.1u
rgate 2 0 4.7Meg
j1 3 2 4 J310
rsrc 4 5 47k
q1 3 4 5 Q2N2222A
q2 5 6 7 Q2N2222A
rb 3 6 2.2k
re 7 0 56
d1 6 8 D1N914
d2 8 0 D1N914
* rload 5 0 1.5k
rload 5 0 50
*
*
..model D1N914 D(Is=0.1p Rs=16 CJO=2p Tt=12n Bv=100)
*
..model J310 NJF(Beta=3.384m Rd=1 Rs=1 Lambda=17m
+ Vto=-3.409 Is=193.9f Cgd=6.2p Pb=1 Fc=.5 Cgs=6.2p
+ Kf=46.34E-18 Af=1)
* National pid=92 case=TO92
*
..model Q2N2222A NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03
+ Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5
+ Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416
+ Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n
+ Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
* National pid=19 case=TO18
*
..control
tran 1u 2m 0 1u
plot v(1), v(5)
fourier 1000 v(5)
..endc
*
..end
*

 

[rickman]

I would not bother to use discrete parts when opamp circuits are so
simple. Since you don't need DC coupling, the common mode range to GND
is not really an issue. You just AC couple the circuit and bias to the
middle of the VDD rail.

The circuit you need is just a voltage follower with an AC coupled
front end. It really couldn't be much simpler.

+--------+
| |
| |\ |
+--|-\ |
C1 | >--+-----o Vout
Vin o---||--+---|+/
| |/
|
\
R1 /
\
/
|
R2 |
Vdd<--\/\/--+----+----+
| |
\ | C2
R3 / ---
\ ---
/ |
| |
V V
R1 > 100 * R2
R2 = R3
R1*C1 < 1 Hz
(R2||R3)*C2 <~ 10 Hz ( optional if your VDD is very stable)

R1 is used to provide a high input impedance while C1 blocks the DC
component. The produce of R1 and C1 form the high pass filter with a
corner some 10x below the 10 Hz freq of interest to get a flat
passband. R1 must also be some 100x greater than the parallel
combination of R2 and R3 to provide good isolation between the bias
voltage and the input voltage.

R2, R3 and C2 form a voltage source and can be replaced by a regulator
if you want improved stability and noise (or don't like the cap C2) of
the bias voltage (which appears at the output like the circuit you
provided). C2 is used to remove Vdd noise since it will appear at the
output at -3dB gain if not filtered.

To get good linearity at the upper end of the freq range, use an op amp
with ~100x unity gain bandwidth or about 200 MHz give or take. Also
pick an op amp that meets your distortion requirements and you are
done.



abhijit wrote:

Greetings!

I have a medium frequency analog signal coming from
a DAC (AD557), but the DAC's output impedance is
too high for my purpose.

So I am trying to design a medium frequency unity gain
buffer amplifier with flat bandwidth from 10Hz to 2MHz,
but I have the following restrictions:

- single 5V supply (split power supply cannot be used)

- input voltage (coming from the DAC) is in the range
0 - 2.6V (it really goes down to 0V)

- so buffer must be able to handle (without distortion)
input voltages really down to 0 volts

- input impedance should be > 50k, preferably fet-input
so that it can be ac-coupled with a 0.1uF cap

- output impedance must be less than 50 ohms

- must have very low distortion

- preferably no large caps

- op-amp is OK provided it is +5V single-supply,
low distortion, and has common-mode input
really going down to negative-rail (ground)

I have designed the circuit below, which gives
a THD of about 0.3% with a 50 ohm load impedance.
Also it may not be very good driving capacitive
loads such as cables. So I am looking for something
with lower distortion and lower output impedance
which can drive capacitive loads with the above
restrictions.

Anyone with more ideas?

Abhijit Dasgupta

============================
Spice file (Berkeley spice3)
============================

Buffer with ac-coupled input to njfet, bipolar output
*
* Improving distortion with a current sink feeding
* the emitter of q1
*
* With rload = 1.5k, THD is minimal (< 0.001%) for
* 0-3V p-p input, but THD increases under load,
* to almost 0.3% when rload = 50 ohms
*
* 3 +--------+-------o vcc +5V
* | |
* |-+ j1 |
* 1 cin 2 | J310 |
* vin o---||---+--->|-+ |
* 0.1uF | | 4 |/ q1
* < +------| 2N2222A
* rgate < | |\.e
* 4.7Meg < < |
* | < rsrc +---o<-----+ vout
* | < 47K | 5 |
* | | | |
* | +--------+ |
* | | |
* 3 | rb 6 |/ q2 |
* vcc -----------/\/\/\-+---| 2N2222A |
* | 2.2K | |\.e |
* | _|_ | |
* | d1 \./ + 7 < external
* | 1N914 -+- | < rload
* | | < < 50 ohms
* | +8 < re |
* | _|_ < 56 ohms |
* | d2 \./ | |
* | 1N914 -+- | |
* | | | |
* 0 +---------+-----+---o<-----+ GND
*
vcc 3 0 dc 5
vin 1 0 dc 0 ac sin(1.5 1.5 1000)
cin 1 2 0.1u
rgate 2 0 4.7Meg
j1 3 2 4 J310
rsrc 4 5 47k
q1 3 4 5 Q2N2222A
q2 5 6 7 Q2N2222A
rb 3 6 2.2k
re 7 0 56
d1 6 8 D1N914
d2 8 0 D1N914
* rload 5 0 1.5k
rload 5 0 50
*
*
.model D1N914 D(Is=0.1p Rs=16 CJO=2p Tt=12n Bv=100)
*
.model J310 NJF(Beta=3.384m Rd=1 Rs=1 Lambda=17m
+ Vto=-3.409 Is=193.9f Cgd=6.2p Pb=1 Fc=.5 Cgs=6.2p
+ Kf=46.34E-18 Af=1)
* National pid=92 case=TO92
*
.model Q2N2222A NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03
+ Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5
+ Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416
+ Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n
+ Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
* National pid=19 case=TO18
*
.control
tran 1u 2m 0 1u
plot v(1), v(5)
fourier 1000 v(5)
.endc
*
.end
*

 

[Larry Brasfield]

"Ken Smith" <kensmith@green.rahul.net> wrote in
message news:d2nbo8$th6$1@blue.rahul.net...

In article <c2A3e.7$WY2.255@news.uswest.net>,
Larry Brasfield <donotspam_larry_brasfield@hotmail.com> wrote:
"Ken Smith" <kensmith@green.rahul.net> wrote in
message news:d2l3t5$30b$1@blue.rahul.net...
In article <V5e3e.10$DQ2.319@news.uswest.net>,
Larry Brasfield <donotspam_larry_brasfield@hotmail.com> wrote:
"Ken Smith" <kensmith@green.rahul.net> wrote in
message news:d2jo57$376$1@blue.rahul.net...
[...]
This is not always true. The loop gain reduces the amplitude of a
harmonic if that harmonic happens to land at a frequency well below the
gain cross over point. If the phase margin is less than 90 degrees, there
is a band where the circuit's gain increases the amplitude of the
harmonic.

I believe you have slightly overstated your case here,
although I agree that, where response peaking occurs,
the harmonic terms falling there are subject to it.

In what way do you think that I've overstated the case? You agree that
those harmonics that land near the gain cross over may be peaked, so
where's the disagreement? Did I miss something?

First, let's assume the usual case of a single dominant pole
and some collection of higher frequency poles in the open
loop response that contribute to reduction of phase margin
from the 90 degrees contributed by the dominant pole.

I believe that this is not actually correct for the op-amp you suggested.

My point was in response to a "not always true" statement
coupled with an ostensibly supporting claim: "If the phase
margin is less than 90 degrees, there is a band where the
circuit's gain increases the amplitude of the harmonic."

To me, it appeared that you were making a general claim,
not one tailored to the specifics of the device I suggested.

Based on its recovery shape, I think that it actually has a zero in its
transfer function but for the purposes of our discussion we do not need to
include that issue.

I don't see that in the datasheet. The open-loop gain plot
is not credible, however, so I'm not sure what it does.

Peaking cannot occur when the loop gain is low enough
to keep the closed loop poles on the real axis.

Remember we are talking about an op-amp with a phase margin of only about
45 degrees. This statement although true as far as it goes does not apply
to the op-amp you have suggested. It does show serious peaking.

We are in noisy agreement, again. But I notice that the
"serious peaking" occurs with 200 pF loading. If you look
at the "Small-Signal Overshoot vs. Load Capacitance"
plot, you will see 5% overshoot at 0 pF, a very benign
response from a stability perspective.

There is
a significant range of loop gain were the phase margin is
less than 90 degrees but the closed loop poles remain
real.

Are you speaking here of the op-amp you suggested? If so, I'll ask you to
state what this range is in this case.

I was speaking in general terms. My point is only that
there is a range of phase margin between where peaking
occurs in a mathematical sense but not to a degree that
presents a stability issue or a real harmonic gain issue.

There is some more range where those poles are
complex but no sigificant peaking occurs.

It does not include the unity gain buffer case under discussion here.

I guess that depends on whether 5% overshoot can
be said to correspond to "significant peaking", or
whether a more difficult load than the OP mentioned
is postulated.

BTW: there is a simple rule for the amount of peaking vs. phase margin.

Yes. It is a rule-of-thumb since its accuracy depends
on where the excess poles actually fall w.r.t. each other.

The OP is driving a cable that drives a load. No mension of a low pass
was made nor could be expected in that case unless the coax. is fairly
long.

I don't know how a low pass got into this.

I introduced it. It is common practice to examine what will happen to a
signal later to see if the distortion is something worth worrying about or
not. If the OP did have a low pass, the distortion products well above
the signal band would matter less and the op-amp specs could be relaxed.
As it is there is no low pass, the specs can't be relaxed.

Ok, I agree with that new point. Much of my own work
on distortion performance has been concerned with odd-
order intermodulation products which fall near the same
frequencies that give rise to them. In those cases, an LPF
does no good at all.

As for "there is no low pass", it is true the OP did not
mention one. But for his precision DAC buffer, it may
be a good idea to have one, perhaps with 1/sinc(f)
correction, depending on his real requirement. And for
all we know, he already has one planned or in place.

suggested", I suggest you
take a look at a simple case where the phase margin is 78.7
degrees.

Now try it at 45 degrees which is what the op-amp you suggested will have.
BTW: 60 degrees is an inportant angle.

If '60' had been in your original general claim rather than '90',
we might have averted this little subdiscussion.

I agree that "some distortion" shows up at levels well
below the slew rate limit, at least if that limit is imposed
by a soft-limiting characteristic, (such as an input pair).
And for some definition of "some", that much distortion
will occur at any significant fraction of the output swing.

If you check out the slew rate specs for op-amps you will find that in
general they are based on the point of total limiting not the point where
distortion passes some low value.

That has been my experience too.

[2 vs 10 MHz, cut]

This distortion
is effectively outside of the feedback loop. Fortunately, for
MOS input stages, (such as the AD8615 has), this distortion
is relatively small. At or near 1.4 MHz, for 1.3 Vp inputs,
the input error is in the neighborhood of 100 mVp, which I
expect is well within the active input range of the stage.

I would not make that bet based on the data sheet. They don't give you
nearly enough information to know what the linear range of the actual
input circuit is. Although the leakage numbers imply that the first
device you hit will be a MOSFET, it does not rule out a bipolar connected
to that MOSFET. Without knowing the actual input topology or having a
specification, you can't say for sure.

From the datasheet alone, I agree. From looking at
their SPICE model, I doubt anything that strange has
been built inside the part.

I would trust that about as far as I can spit it. I've been burned often
enough to know that if the datasheet doesn't say it watch out.

Once upon a time, I thought all design should be done
so as to guarantee the required performance based on
nothing but worst-case datasheet guarantees. Since
then, I've had to become more realistic. I do not deny
that prudence has a place in that calculus, but there are
too many device characteristics affecting large signal
performance to demand they all be guaranteed within
the datasheet specifications.

[more 2 vs 10 MHz, cut]

The typical curve show huge peaking of Zout at about 30MHz. Since no
min/max numbers are given you can't trust it.

I do not see the relevance of the 30 MHz value. That
would correspond to the 15th harmonic of the highest
frequency mentioned by the OP. The same chart shows
that the open loop output impedance is about 45 Ohms
in the frequency range mentioned in the OP's post.

The OP-speced 50 Ohms of impedance. The huge peaking points out that
small variations in device parameters will change the impedance wildly.

What you call "huge peaking" represents a closed-loop
output impedance about 3 times the open-loop output
impedance, and it occurs well outside the OP's stated
bandwidth. The effect occurs because the feedback
is becoming positive due to the phase margin situation.
The stability of that effect is just as reliable as the stability
of the unity gain connected op-amp. While I do not have
unlimited faith in such matters, I do not believe Analog
Devices sells many op-amps that are ready to become
oscillators when used per their recommendations.

(2) The THD+N is only shown up to 20KHz, therefor we know that it goes bad
at about 21KHz.

Not at all obvious, except maybe to cynics.

... and those who have been bitten. The cut off point is way lower than
the devices specified bandwidth etc. On the early data sheets, the
LT1028's noise spec stopped at about 20KHz too. Guess what.

I don't recall the LT1028 doing anything strange noise-wise
at any frequency. I've used it where noise mattered a lot,
and looked at it quite carefully, so I need not guess about it.

Would you
not agree that such a cutoff in the chart may reflect either
the presumed interest of those considering the part for
audio applications, or the limits of some instrument built
for that market? Surely you do not believe that some
strange circuitry is built into a 20 MHz GBW part that
really sends it South near 21 KHz.

Ok, mayby its 22KHz. Until I see it on a datasheet, I'm not going to
trust it. Harris made some very fast op-amps, back in the stone age, that
had two internal paths. It had a very fast high distortion,low gain path
and a slower low distortion, high gain path. At the point where which
path dominated changed, the distortion got bad in a hurry.

We will have to disagree on the appropriate skepticism here.
But to validate your point, I would insist on seeing some
real parts, especially where distortion is a major concern.

(3) It rings badly with a 200pF load.

If he is driving a non-50 Ohm cable between his amplifier
and his 50 Ohm load, or more than a few feet of cable
with a load resistance much higher than 50 Ohms, then
that ringing could be a problem. We still have seen no
answer to my question regarding the cable situation. I
dare say the issue is getting attention here far in excess
of the OP's interest or the available facts.

I think the OP was hoping for a simple answer and since he didn't get one
he bailed out on us.

Maybe he got a simple answer, "use an op-amp", and is
off looking into it, with better knowledge of what he needs
than we have been privy to.

example, with suitable care in its application, and a bead
between the device and a misterminated cable, he would

Beads can cause measurable distortion. I'd suggest a resistor since he
can stand a 50 Ohm output.

Using only a +5V supply and delivering 2.6 Vpp to his 50
Ohm load, I think headroom could become an issue if that
resistor got near the load value.

The bead I had in mind would be to isolate the reactive
load at frequencies where it could destabilize that 1 GHz
GBW amplifier. A bead that only cuts in a 100 MHz or
so is not going to have much effect at 2 MHz and below.
It need not be operated in its nonlinear region.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[Ken Smith]

In article <yA_3e.59$D53.1113@news.uswest.net>,
Larry Brasfield <donotspam_larry_brasfield@hotmail.com> wrote:
[...]

Your "realistic" would be called "sloppy beyond all reason" in the
industry I work in. In the "audio" business, and a lot of other consumer
stuff, no-one will ever know if 10% of the units don't really meet spec.

That is silly. I am stating nothing more than the commonly
understood fact that some parameters upon which a design
relies are not found in the min or max columns of a datasheet.

No-one where I work would use a typical noise or distortion spec as what
to expect in the design. If the typical is 10 times better than the
circuit needs, the typical would be used as an indication but there would
be nervousness.

If you believe that has never happened in your industry, or
only happens when "sloppy" engineering is done, then you
have led a life sheltered from reality.

Like I said "it would be *called* sloppy". I have engaged in some such
name calling directly to our customer base when we discovered that the
other guys had a spec that only worked as a typical.


[... LT1028 ...]

That frequency is a ways beyond where I was looking.
(The application was delay control in an analog phased
array beamformer, where an LPF was necessary to
keep noise at such frequencies out of the RF signal.)
I suppose that bump could be called strange, although
if you look at the bias current cancellation scheme in
that part, it is not too surprising that it would happen.

Oh! I see nothing in the bias current cancellation that would make the
increase I observed.

--
--
kensmith@rahul.net forging knowledge