unexpected results from conditional operator in for loop

[gorjusborg]

I ran into a problem recently where I was doing this:

// Increment index from 0-9, but skip 4
for ( integer i=0; i < 10; i = i + (i == 'd3) ? 2 : 1 ) begin
...
end

When I would run in vcs7.2.1R17, the simulation would increment from 1
to 2, but would not increment to 3 or above. I would not expect this
behavior.

Is this a Verilog language quirk? Or a simulator specific bug?
(In a related question, can anyone point me to an LRM covering
Verilog2001?)

Brandon Atkinson
Tundra Semiconductor Corp
brandon.atkinsonATmycompany.com

 

[johnp]

Brandon -

I believe you need to add some parenthesis since the
"+" operator is higher precidence than the ternary "?".

I believe your code is:
i = (i + (i == 'd3)) ? 2 : 1

I think you want
i = i + (i == 'd3 ? 2 : 1)

John Providenza

gorjusborg wrote:

I ran into a problem recently where I was doing this:

// Increment index from 0-9, but skip 4
for ( integer i=0; i < 10; i = i + (i == 'd3) ? 2 : 1 ) begin
...
end

When I would run in vcs7.2.1R17, the simulation would increment from 1
to 2, but would not increment to 3 or above. I would not expect this
behavior.

Is this a Verilog language quirk? Or a simulator specific bug?
(In a related question, can anyone point me to an LRM covering
Verilog2001?)

Brandon Atkinson
Tundra Semiconductor Corp
brandon.atkinsonATmycompany.com

 

[gorjusborg]

John,

Thanks for solving my problem.

Sometimes I wish I always had a 'fresh pair of eyes' lying around!

Brandon Atkinson
johnp wrote:

Brandon -

I believe you need to add some parenthesis since the
"+" operator is higher precidence than the ternary "?".

I believe your code is:
i = (i + (i == 'd3)) ? 2 : 1

I think you want
i = i + (i == 'd3 ? 2 : 1)

John Providenza

gorjusborg wrote:
I ran into a problem recently where I was doing this:

// Increment index from 0-9, but skip 4
for ( integer i=0; i < 10; i = i + (i == 'd3) ? 2 : 1 ) begin
...
end

When I would run in vcs7.2.1R17, the simulation would increment from 1
to 2, but would not increment to 3 or above. I would not expect this
behavior.

Is this a Verilog language quirk? Or a simulator specific bug?
(In a related question, can anyone point me to an LRM covering
Verilog2001?)

Brandon Atkinson
Tundra Semiconductor Corp
brandon.atkinsonATmycompany.com