undeclared loop variable

B

Brad Smallridge

Guest
It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?

for col in 1 to 16 loop
wait for clkperiod;
end loop;
 
"Brad Smallridge" <bradsmallridge@dslextreme.com> writes:

It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?
VHDL considers the iteration variable to be constant for each pass
through the loop.

Regards,


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
 
Brad Smallridge wrote:

It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?

for col in 1 to 16 loop
wait for clkperiod;
end loop;

the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop
 
The looping index is considered an implicit variable in vhdl and is
local to the for loop.
 
Neo wrote:
The looping index is considered an implicit variable in vhdl and is
local to the for loop.
In fact as Kai pointed out, the loop index is a constant.

All that means in practice is that you can't, for instance, do

col := 10;

inside the loop.

regards
Alan

--

Alan Fitch
Doulos Ltd
http://www.doulos.com
 
My Name wrote:
for col in 1 to 16 loop
wait for clkperiod;
end loop;

the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop
I don't see that as a drawback. What value would you expect "col" to
have outside the loop anyway?

Paul.
 
On Thu, 24 Mar 2005 00:30:14 -0700, My Name <email@address.com> wrote:

[VHDL 'for' loop index is an implied constant within the loop...]
the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop
Can you show me an example of this kind of thing that I could
read and yet still retain my lunch?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Paul Uiterlinden wrote:
My Name wrote:


for col in 1 to 16 loop
wait for clkperiod;
end loop;


the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop


I don't see that as a drawback. What value would you expect "col" to
have outside the loop anyway?

Paul.

well, neither do I really.
 

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