B
Brad Smallridge
Guest
It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?
for col in 1 to 16 loop
wait for clkperiod;
end loop;
declaring col as a signal or a variable or anything.
What is vhdl doing with col?
for col in 1 to 16 loop
wait for clkperiod;
end loop;