Unconstrained ports for synthesis

[Mohammed A khader]

Hi all,

I am having a component Multiplier with unconstrained ports. But this
is not my top_level_entity and ports are implicity constrained while
instanciating this component.

It simulates well but while synthezing Quartus says that ports must be
constrained. I think that Quartus could infer it from instanciation
syntax. Is there any solution to get around it

Thanks.

-- Mohammed A Khader.

 

[Mohammed A Khader]

Hi,

-- Error messages are......

Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26):
ports must be constrained
Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(27): ports
must be constrained
Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(28): ports
must be constrained
Error: Can't elaborate user hierarchy
"Core:Core_Map|Datapathatapath_Map"
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0
warnings
Error: Processing ended: Wed Apr 20 16:33:52 2005
Error: Elapsed time: 00:00:05

-- My Multiplier component is .........
entity Multiplier_Synth is
port(
Op1 : in signed; -- Operator 1
Op2 : in signed; -- Operator 2
Mult_Out : out signed -- Multiplication Result
);
end entity Multiplier_Synth;

architecture Multiplier_Synth_Arch of Multiplier_Synth is
begin
Mult_Out <= Op1 * Op2;
end architecture Multiplier_Synth_Arch;

-- And it has been instantiated in an entity called Datapath_Map as
.......

signal Mux1_Out : WORD20; -- Output of Mux1
signal Mux2_Out : WORD; -- Output of Mux2
signal Mult_Out : signed(39 downto 0); -- Multiplier Output

Multiplier_Map : entity work.Multiplier_Synth(Multiplier_Synth_Arch)
port map(
Op1 => Mux1_Out,
Op2 => Mux2_Out,
Mult_Out => Mult_Out
);

Mux1_Out , Mux2_Out and Mult_Out are constrained signals . Hence
Op1,Op2,Mult_Out implicitly can be constrained by bit length of
20,20,40 respectively.

Thanks..

-- Mohammed A Khader.

 

[Subroto Datta]

Hello Mohammed,

We will be adding support for unconstrained entity ports in 5.1,
due out later this year (we need to get 5.0 out first ). In the
interim please use the generic approach suggested by Ralf.

Hope this helps,
Subroto Datta
Altera Corp.