D
Debjit Pal
Guest
Dear All,
I like to write a Verilog-AMS model with the following purpose:
Purpose:
After detection of a posedge of start, expr will be checked for a delay period. If expr remains asserted for the delay period, then at the end of the delay time, match signal will be asserted and will be kept high for KeepMatchHighTime duration. But if expr is not TRUE after start is detected, immediately fail will be asserted and will be kept high for KeepMatchHighTime duration. If a match pulse arrives before the check of previous match pulse is complete, another thread of checking of expr will be generated. For that I have written the following code. But the code is unable to create multiple checks for start events which arrived before completion of checks for the previous start pulses.
Code:
##############################################################
//Verilog-AMS HDL for "AMS_Verification_Library", "GlobalOperator" "verilogams"
`include "constants.vams"
`include "disciplines.vams"
`default_discipline logic
module CadenceGlobalOperatorFork (start, expr, match, fail);
input start, expr;
output match, fail;
wire start, expr;
reg match, fail;
event trig_match ;
event trig_fail ;
parameter real TimeTolerance = 1e-9 from [-1:1];
parameter real delay = 1u from [0:inf);
parameter real KeepMatchHighTime = 10n from [1e-12:1e-6];
parameter integer verbose = 0 from [0:1];
parameter PropertyName = "Property";
integer NumberOfStart, MaxNumberOfStart;
integer NumberOfMatch;
integer FileHandleProperty;
integer SetExpr;
real TimeOfStart[0:100];
real TimeOfMatch[0:100];
real TimeOfFail[0:100];
real TimeEndExpr;
initial begin
match = 1'b0;;
fail = 1'b0;
NumberOfStart = 0;
MaxNumberOfStart = 50;
NumberOfMatch = 0;
SetExpr = 0;
TimeEndExpr = 0.0;
NumberOfStart = 0;
end
always @(expr)
begin
if(expr)
begin
SetExpr = 1;
end
else
begin
SetExpr = 0;
end
end
always @ (trig_match )
begin
TimeOfMatch[NumberOfStart] = $abstime;
match = 1'b1;
FileHandleProperty = $fopen("PropertySatisfiedLog.txt","a");
$fwrite(FileHandleProperty, "%s started checking @ %e and matched @ %e.\n", PropertyName, TimeOfStart[NumberOfStart], TimeOfStart[NumberOfStart]);
$fclose(FileHandleProperty);
if (verbose)
begin
$display("%s started checking @ %e and matched @ %e.", PropertyName, TimeOfStart[NumberOfStart], TimeOfMatch[NumberOfStart]);
end
@(cross(($abstime - (TimeOfMatch[NumberOfStart] + KeepMatchHighTime)), +1, TimeTolerance)) ;
match = 1'b0;
end
always @ (trig_fail )
begin
fail = 1'b1;
TimeOfFail[NumberOfStart] = $abstime;
FileHandleProperty = $fopen("PropertySatisfiedLog.txt", "a");
$fwrite(FileHandleProperty, "%s started checking @ %e and failed @ %e.\n", PropertyName, TimeOfStart[NumberOfStart], TimeOfFail[NumberOfStart]);
$fclose(FileHandleProperty);
if (verbose)
begin
$display("%s started checking @ %e and failed @ %e.", PropertyName, TimeOfStart[NumberOfStart] , TimeOfFail[NumberOfStart]);
end
@(cross(($abstime - (TimeOfFail[NumberOfStart] + KeepMatchHighTime)), +1, TimeTolerance));
fail = 1'b0;
end
always fork:main
@(posedge start)
begin
if (NumberOfStart == MaxNumberOfStart)
NumberOfStart = 0;
else
NumberOfStart = NumberOfStart + 1;
TimeOfStart[NumberOfStart] = $abstime;
$display("%d start pulse detected.", NumberOfStart);
if (expr)
begin
$display("For %d start pulse entered if(expr).", NumberOfStart);
fork
begin : test_delay_time
@(cross(($abstime - (TimeOfStart[NumberOfStart] + delay)), +1, TimeTolerance));
-> trig_match;
disable test_negedge_expr ;
end
begin : test_negedge_expr
wait (!expr) ;
if (($abstime - TimeOfStart[NumberOfStart]) > delay )
->trig_match ;
else
->trig_fail ;
disable test_delay_time;
end
join
end
else
->trig_fail ;
end
join
endmodule
### Code Ends###
Can you please suggest the mistake I am making? Thanks in advance for your kind support.
Yours sincerely,
Debjit Pal.
I like to write a Verilog-AMS model with the following purpose:
Purpose:
After detection of a posedge of start, expr will be checked for a delay period. If expr remains asserted for the delay period, then at the end of the delay time, match signal will be asserted and will be kept high for KeepMatchHighTime duration. But if expr is not TRUE after start is detected, immediately fail will be asserted and will be kept high for KeepMatchHighTime duration. If a match pulse arrives before the check of previous match pulse is complete, another thread of checking of expr will be generated. For that I have written the following code. But the code is unable to create multiple checks for start events which arrived before completion of checks for the previous start pulses.
Code:
##############################################################
//Verilog-AMS HDL for "AMS_Verification_Library", "GlobalOperator" "verilogams"
`include "constants.vams"
`include "disciplines.vams"
`default_discipline logic
module CadenceGlobalOperatorFork (start, expr, match, fail);
input start, expr;
output match, fail;
wire start, expr;
reg match, fail;
event trig_match ;
event trig_fail ;
parameter real TimeTolerance = 1e-9 from [-1:1];
parameter real delay = 1u from [0:inf);
parameter real KeepMatchHighTime = 10n from [1e-12:1e-6];
parameter integer verbose = 0 from [0:1];
parameter PropertyName = "Property";
integer NumberOfStart, MaxNumberOfStart;
integer NumberOfMatch;
integer FileHandleProperty;
integer SetExpr;
real TimeOfStart[0:100];
real TimeOfMatch[0:100];
real TimeOfFail[0:100];
real TimeEndExpr;
initial begin
match = 1'b0;;
fail = 1'b0;
NumberOfStart = 0;
MaxNumberOfStart = 50;
NumberOfMatch = 0;
SetExpr = 0;
TimeEndExpr = 0.0;
NumberOfStart = 0;
end
always @(expr)
begin
if(expr)
begin
SetExpr = 1;
end
else
begin
SetExpr = 0;
end
end
always @ (trig_match )
begin
TimeOfMatch[NumberOfStart] = $abstime;
match = 1'b1;
FileHandleProperty = $fopen("PropertySatisfiedLog.txt","a");
$fwrite(FileHandleProperty, "%s started checking @ %e and matched @ %e.\n", PropertyName, TimeOfStart[NumberOfStart], TimeOfStart[NumberOfStart]);
$fclose(FileHandleProperty);
if (verbose)
begin
$display("%s started checking @ %e and matched @ %e.", PropertyName, TimeOfStart[NumberOfStart], TimeOfMatch[NumberOfStart]);
end
@(cross(($abstime - (TimeOfMatch[NumberOfStart] + KeepMatchHighTime)), +1, TimeTolerance)) ;
match = 1'b0;
end
always @ (trig_fail )
begin
fail = 1'b1;
TimeOfFail[NumberOfStart] = $abstime;
FileHandleProperty = $fopen("PropertySatisfiedLog.txt", "a");
$fwrite(FileHandleProperty, "%s started checking @ %e and failed @ %e.\n", PropertyName, TimeOfStart[NumberOfStart], TimeOfFail[NumberOfStart]);
$fclose(FileHandleProperty);
if (verbose)
begin
$display("%s started checking @ %e and failed @ %e.", PropertyName, TimeOfStart[NumberOfStart] , TimeOfFail[NumberOfStart]);
end
@(cross(($abstime - (TimeOfFail[NumberOfStart] + KeepMatchHighTime)), +1, TimeTolerance));
fail = 1'b0;
end
always fork:main
@(posedge start)
begin
if (NumberOfStart == MaxNumberOfStart)
NumberOfStart = 0;
else
NumberOfStart = NumberOfStart + 1;
TimeOfStart[NumberOfStart] = $abstime;
$display("%d start pulse detected.", NumberOfStart);
if (expr)
begin
$display("For %d start pulse entered if(expr).", NumberOfStart);
fork
begin : test_delay_time
@(cross(($abstime - (TimeOfStart[NumberOfStart] + delay)), +1, TimeTolerance));
-> trig_match;
disable test_negedge_expr ;
end
begin : test_negedge_expr
wait (!expr) ;
if (($abstime - TimeOfStart[NumberOfStart]) > delay )
->trig_match ;
else
->trig_fail ;
disable test_delay_time;
end
join
end
else
->trig_fail ;
end
join
endmodule
### Code Ends###
Can you please suggest the mistake I am making? Thanks in advance for your kind support.
Yours sincerely,
Debjit Pal.