unable to compile fphdl package (www.eda.org/fphdl)

Hello all,

I downloaded the following packages from www.eda.org/fphdl

fphdl_base_pkg.vhd - Base package (named "fphdl_base_pkg")
fphdl_base_pkg_body.vhd - Base package body (synthesizable)

This package uses fixed_pkg . Which I downloaded from
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html

When I compiled the fixed_pkg package declearation, it gave following
errors

#Error: COMP96_0122: fixed_pkg.vhd : (812, 3): Symbol
"to_StdLogicVector" has already been declared in this region.
# Error: COMP96_0122: fixed_pkg.vhd : (813, 3): Symbol
"to_Std_Logic_Vector" has already been declared in this region.
# Error: COMP96_0122: fixed_pkg.vhd : (912, 3): Symbol "bwrite" has
already been declared in this region.

On googling for the above error I got a message at this link
http://www.electronic2.com/detail-10095547.html
which said to remove the ALIAS in the package declearation. It worked.

Again when i compiled the body of the fixed_pkg , for lines of this
kind :---

constant NAU : UNSIGNED(0 downto 1) := (others => '0');

following warnings came----

warning: COMP96_0119: fixed_pkg_body.vhd : (2610, 37): The range is
"null range".

When I changed the line to :----

constant NAU : UNSIGNED(0 to 1) := (others => '0');

the warning disappeared.

Now my questions are :

(1) why those ALIAS were kept there??? Were they kept there
delibrately.

(2)Does this below mentioned statement make any sense ?? what is (0
downto 1) ???
constant NAU : UNSIGNED(0 downto 1) := (others => '0');

(3) I want to use fphdl package to get a synthesisable LOG function in
my VHDL. Is there a better method for it, or am on right track ??

with regards
ved

 

David and Mariusz, thanks for the reply

David,
I need Ln only. I will try to follow what u have told.

Mariusz,
I am still struggling to compile the package !
I am using students version of Active-HDL. So i don't think that i will
be getting any updates from support.
What if i download Active-HDL all over again?
Will I be able to compile and use the package after downloading a new
Active-HDL ?

Mariusz wrote:

There were some issues with VHDL compiler and have been resolved now.
Contact Aldec support http://support.aldec.com to obtain an update that
will solve your compilatin problems.

Regards,
Mariusz