Unable to assign array element

[Daku]

Could some verilog guru please help me ? I am using ICarus Verilog
0.9.1. Using a very simple program, I am trying to assign to and read
from integer arrays. I declare this array as integer 'indexArray[0:MAX
-1];'
In the 'initial' block, I set all array elements to 0, and then inside
an 'always' block, I try to re-assign certain array elements,
depending on certain conditions. This fails. There are no compilation
errors.
Any suggestions, help would be greatly appreciated. Thanks in advance
for your help. The source code file contents are attached for
reference:

module arraytb;
parameter MAX = 10;

reg clock;
integer indexArray[0:MAX-1];
integer i;
integer j;
integer num;

initial
begin
$dumpfile("arraytb.vcd");
$dumpvars(1, arraytb);
clock = 1;
num = 0;
j = 0;
for(i = 0; i < MAX-1; i = i+1) indexArray = 0;
#100 $finish;
end

always
begin
#5 clock = !clock;
end

always @ (posedge clock)
begin
if(num < MAX)
$display("clock= %b num = %d j = %d array value=%d\n", clock,
num, j, indexArray[j]);
indexArray[j] = 1; //Does not work !!!
j = j+1;
num = num + 1;
end

endmodule

 

[pallav]

On Sep 12, 11:12 am, Daku <dakup...@gmail.com> wrote:

Could some verilog guru please help me ? I am using ICarus Verilog
0.9.1. Using a very simple program, I am trying to assign to and read
from integer arrays. I declare this array as integer 'indexArray[0:MAX
-1];'
In the 'initial' block, I set all array elements to 0, and then inside
an 'always' block, I try to re-assign certain array elements,
depending on certain conditions. This fails. There are no compilation
errors.
Any suggestions, help would be greatly appreciated. Thanks in advance
for your help. The source code file contents are attached for
reference:

module arraytb;
parameter MAX = 10;

reg clock;
integer indexArray[0:MAX-1];
integer i;
integer j;
integer num;

initial
  begin
   $dumpfile("arraytb.vcd");
   $dumpvars(1, arraytb);
   clock = 1;
   num = 0;
    j   = 0;
   for(i = 0; i < MAX-1; i = i+1) indexArray = 0;
   #100 $finish;
  end

always
 begin
  #5 clock = !clock;
end

always @ (posedge clock)
  begin
   if(num < MAX)
    $display("clock= %b num = %d j = %d array  value=%d\n", clock,
num, j, indexArray[j]);
    indexArray[j] = 1; //Does not work !!!
    j = j+1;
    num = num + 1;
   end

endmodule

Its working. but you are not seeing the result because you print out
the old value and then uddate it.
Put indexArray[j] = 1 before the $display command.

 

[Daku]

On Sep 13, 12:59 am, pallav <pallavgu...@gmail.com> wrote:

On Sep 12, 11:12 am, Daku <dakup...@gmail.com> wrote:



Could some verilog guru please help me ? I am using ICarus Verilog
0.9.1. Using a very simple program, I am trying to assign to and read
from integer arrays. I declare this array as integer 'indexArray[0:MAX
-1];'
In the 'initial' block, I set all array elements to 0, and then inside
an 'always' block, I try to re-assign certain array elements,
depending on certain conditions. This fails. There are no compilation
errors.
Any suggestions, help would be greatly appreciated. Thanks in advance
for your help. The source code file contents are attached for
reference:

module arraytb;
parameter MAX = 10;

reg clock;
integer indexArray[0:MAX-1];
integer i;
integer j;
integer num;

initial
begin
$dumpfile("arraytb.vcd");
$dumpvars(1, arraytb);
clock = 1;
num = 0;
j = 0;
for(i = 0; i < MAX-1; i = i+1) indexArray = 0;
#100 $finish;
end

always
begin
#5 clock = !clock;
end

always @ (posedge clock)
begin
if(num < MAX)
$display("clock= %b num = %d j = %d array value=%d\n", clock,
num, j, indexArray[j]);
indexArray[j] = 1; //Does not work !!!
j = j+1;
num = num + 1;
end

endmodule

Its working. but you are not seeing the result because you print out
the old value and then uddate it.
Put indexArray[j] = 1 before the $display command.

I am afraid I tried your idea already before making my previous post,
and it did not work/

 

[perich]

Hi Daku,

Being relatively new to verilog myself, I am not really sure what the
problem is, but I suspect the problem has something to do with j not
being assigned before being used inside the always statement.

Anyway, this description should work with Icarus (I tested it):
(I used indexArray[j] = j; just to indicate this description works).

module arraytb;
parameter MAX = 10;

reg clock;
integer indexArray[0:MAX-1];
integer i;
integer j;
integer num;

initial
begin
$dumpfile("arraytb.vcd");
$dumpvars(1, arraytb);
clock = 1;
num = 0;
j = 0;
for(i = 0; i < MAX; i = i+1) indexArray = 0;
#150 $finish;
end

always
begin
#5 clock = !clock;
end

always @ (posedge clock)
begin
if(num < MAX)
j=num;
indexArray[j] = j;
$display("clock= %b num = %d j = %d array value=%d\n", clock,
num, j, indexArray[j]);
num = num + 1;
end

endmodule

 

[perich]

Hi Daku,

I looked into it a little better and pallav is absolutely right about
first updating the array value before printing it.
You should also use 'begin' and 'end' keywords when your if-statement
has more than one expression.

This time I used "indexArray[j] = j+1;" to check if indexArray[0] is
also updated from it's initial value.

This should work:

module arraytb;
parameter MAX = 10;

reg clock;
integer indexArray[0:MAX-1];
integer i;
integer j;
integer num;

initial
begin

$dumpfile("arraytb.vcd");
$dumpvars(1, arraytb);

clock = 1;
num = 0;
j = 0;

for(i = 0; i < MAX; i = i+1)
begin
indexArray = 0;
end

end

always
begin
#5 clock = !clock;
end

always @ (posedge clock)
begin
if(num < MAX)
begin
indexArray[j] = j+1;
$display("clock= %2b, num = %2d, j = %2d, array_value=%2d\n",
clock, num, j, indexArray[j]);
j=j+1;
num=num+1;
end
else
begin
#10 $finish;
end

end

endmodule