ultrasim w/ VCD and hierarchical mapping

[oliver]

Has anyone ever used verilog value change dump stimuli (VCD file) in
ultrasim with hierarchical
mapping to set stimuli to signals in lower levels of analog netlists?


I managed to use a VCD file with flat mapping of stimuli to signals at
the netlist toplevel, but
when I try mapping a VCD file hierarchically (.hier 1 in the .info
file), the simulation runs,
but the stimuli is not taken into account.

Here's a testcase with the signal I've defined in the .vcd file:
...
$scope module bench_analog_top $end
$var wire 1 ! xosc16M_clkvalid $end
$upscope $end
$enddefinitions $end
#10000
$dumpvars
b0 !
$end
#20000
b1 !
...

and the .info file:

.alias *[*] *_*
.hier 1
.scope bench_analog_top
.vih 2.7 xosc16M_clkvalid
.in xosc16M_clkvalid
.alias xosc16M_clkvalid Ianalog_top.xosc16M_clkvalid

where "Ianalog" is an instance of the cell "analog_top" in the
testbench "bench_analog_top".
"xosc16M_clkvalid" is a pin of cell "analog_top".


Any idea what's wrong?

Thanks.
Oliver