ucf impact to synplify pro

W

william

Guest
Hi,

I am using synplify pro.
In synplify constraint file I can add in the pin assignment for physica
FPGA mapping.
but I can not tell the difference add and not add. I did not se
significant timing improve or related information embedded into outpu
edf.

is it the pin assignment really help timing/sythesis for final out com
result?



---------------------------------------
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On Nov 5, 1:06 pm, "william" <cuteworm@n_o_s_p_a_m.wildmail.com>
wrote:
is it the pin assignment really help timing/synthesis for final out come
result?
Why would you expect it to?

Location constraints are just embedded into the netlist during
synthesis.
 
"william" <cuteworm@n_o_s_p_a_m.wildmail.com> wrote in message news:pIKdnYImkMdU_knRnZ2dnUVZ_s2dnZ2d@giganews.com...
Hi,

I am using synplify pro.
In synplify constraint file I can add in the pin assignment for physical
FPGA mapping.
but I can not tell the difference add and not add. I did not see
significant timing improve or related information embedded into output
edf.

is it the pin assignment really help timing/sythesis for final out come
result?
pin location constraints in the synplify .sdc file are forward annotated to the .ncf file, assuming the option to generate a .ncf
file is set in the synplify project. The .ncf file is then read by ISE and the signal is placed as directed. I don't think a pin
loc will make any change to an edif file, but I've never looked to see.

--steve
 
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