uart.vhd compile problems

[Mike Treseler]

Brandon Brown wrote:

I'm trying to compile your uart.vhd code
in ModelSim and I get the following error:
uart.vhd(85): near "main": expecting: BEGIN
Any ideas? I'm new to VHDL simulation and ModelSim in general.

Maybe some of the lines wrapped.
Check it in a text editor.
Then click up a shell and type

vcom

and make sure you get the usage message, then

vcom uart.vhd test_uart.vhd

Thank you very much for providing these files btw, they are very useful.

You are welcome.
Sometimes I use them too.

-- Mike Treseler