Types of Verilog

[Yero]

I'm a bit confused as to the hierarchy of levels of Verilog.
From my understanding, I've been refered to the following sub-categories
of Verilog in classes. I'm not sure if they're all distinct, or if one's
the subset of another, etc.

Verilog RTL (Register Transer Level/Logic?)
Synthesizable Verilog
Behavioral Verilog
Functional Verilog
Verilog HDL
VHDL

Can anyone clue me in?
Thanks.
--
* Character is forged on the anvil of adversity.
- Mr. Panicucci
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Yero Dermenjian
ydermenj@andrew.cmu.edu
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[y_p_w]

Yero wrote:

I'm a bit confused as to the hierarchy of levels of Verilog.
From my understanding, I've been refered to the following
sub-categories of Verilog in classes. I'm not sure if they're all
distinct, or if one's the subset of another, etc.

Verilog RTL (Register Transer Level/Logic?)
That's simply an abstraction of sequential elements (registers/

latches) and combinational logic (next-state and/or random logic).

Synthesizable Verilog Behavioral Verilog
Certain elements that work in simulation can't be converted into

gates by synthesis tools. There are shortcuts that can be taken
in testbenches, since they don't have to be synthesized. Actually,
there isn't that much difference between this and Verilog RTL.

Functional Verilog
I have no idea what this means.

Verilog HDL
Verilog is a hardware description language. This covers everything

in the language.

VHDL
VHDL is not Verilog. It's a separate HDL initially developed for

the US Defense Dept, with different syntax.

 

[pablo aimar]

Functional Verilog
Any verilog code can be said to be functional. But i think

functional verilog
is the one that is written just to emulate the functionality of the
design(no worry wheather it is synthesizable or not). For example if
you take any memory
companies (micron, cypress, ..) they have functional models that user
can use during verification but not synthesizable.

Regards
rao