type errors in vhdl

[lucky]

in vhdl
I am not able to assign x"ab" to a signal diclared as say
a:std_logic_vector(7 down to 0)
the error is type error bit vector can not be assigned to
std_logic_vector

what is possible solution?

 

[Jonathan Bromley]

On 1 Sep 2006 07:40:02 -0700, "lucky" <atluricharan@gmail.com> wrote:

in vhdl
I am not able to assign x"ab" to a signal diclared as say
a:std_logic_vector(7 down to 0)
the error is type error bit vector can not be assigned to
std_logic_vector

what is possible solution?

Make sure your VHDL compiler has VHDL-93 or VHDL-2002 enabled.
The X"AB" syntax worked only for bit-vectors in VHDL-87, but was
extended to other vector types in VHDL-93.
--
Jonathan Bromley, Consultant

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