A
Ahmad
Guest
Hi all,
I hope any one can help me with this error. I get this eror everytime:
"cic_order3_testbench_struct.vhd",line 82: Error, type error at
'difout_2'. Needed type 'signed'.
I can't understand what this error is?!
Note: cic_order3 works alone, just be connecting its output to a port
in the testbench it gives this error
-- renoir header_start
--
-- VHDL Entity integrator.CIC_order3_TestBench.symbol
--
-- Created:
-- by - ahmad.UNKNOWN (KIMO-DESKTOP)
-- at - 13:00:30 18-Sep-03
--
-- Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
--
-- renoir header_end
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY CIC_order3_TestBench IS
PORT(
Clk : IN std_logic ;
Reset : IN std_logic ;
combout : OUT signed (15 DOWNTO 0)
);
-- Declarations
END CIC_order3_TestBench ;
-- renoir interface_end
--
-- VHDL Architecture integrator.CIC_order3_TestBench.struct
--
-- Created:
-- by - ahmad.UNKNOWN (KIMO-DESKTOP)
-- at - 13:00:30 18-Sep-03
--
-- Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY std ;
USE std.textio.ALL;
LIBRARY integrator;
ARCHITECTURE struct OF CIC_order3_TestBench IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL TRout : signed(15 downto 0);
-- Component Declarations
COMPONENT CIC_order3
PORT (
Clk : IN std_logic ;
IntIn : IN signed (15 downto 0);
Reset : IN std_logic ;
DifOut_2 : OUT signed (15 downto 0)
);
END COMPONENT;
COMPONENT TextReader
PORT (
Clk : IN std_logic ;
Reset : IN std_logic ;
TRout : OUT signed (15 downto 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : CIC_order3 USE ENTITY integrator.CIC_order3;
FOR ALL : TextReader USE ENTITY integrator.TextReader;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I0 : CIC_order3
PORT MAP (
Clk => Clk,
IntIn => TRout,
Reset => Reset,
DifOut_2 => combout --THIS IS THE ERROR
);
I1 : TextReader
PORT MAP (
Clk => Clk,
Reset => Reset,
TRout => TRout
);
END struct;
I hope any one can help me with this error. I get this eror everytime:
"cic_order3_testbench_struct.vhd",line 82: Error, type error at
'difout_2'. Needed type 'signed'.
I can't understand what this error is?!
Note: cic_order3 works alone, just be connecting its output to a port
in the testbench it gives this error
-- renoir header_start
--
-- VHDL Entity integrator.CIC_order3_TestBench.symbol
--
-- Created:
-- by - ahmad.UNKNOWN (KIMO-DESKTOP)
-- at - 13:00:30 18-Sep-03
--
-- Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
--
-- renoir header_end
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY CIC_order3_TestBench IS
PORT(
Clk : IN std_logic ;
Reset : IN std_logic ;
combout : OUT signed (15 DOWNTO 0)
);
-- Declarations
END CIC_order3_TestBench ;
-- renoir interface_end
--
-- VHDL Architecture integrator.CIC_order3_TestBench.struct
--
-- Created:
-- by - ahmad.UNKNOWN (KIMO-DESKTOP)
-- at - 13:00:30 18-Sep-03
--
-- Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY std ;
USE std.textio.ALL;
LIBRARY integrator;
ARCHITECTURE struct OF CIC_order3_TestBench IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL TRout : signed(15 downto 0);
-- Component Declarations
COMPONENT CIC_order3
PORT (
Clk : IN std_logic ;
IntIn : IN signed (15 downto 0);
Reset : IN std_logic ;
DifOut_2 : OUT signed (15 downto 0)
);
END COMPONENT;
COMPONENT TextReader
PORT (
Clk : IN std_logic ;
Reset : IN std_logic ;
TRout : OUT signed (15 downto 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : CIC_order3 USE ENTITY integrator.CIC_order3;
FOR ALL : TextReader USE ENTITY integrator.TextReader;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I0 : CIC_order3
PORT MAP (
Clk => Clk,
IntIn => TRout,
Reset => Reset,
DifOut_2 => combout --THIS IS THE ERROR
);
I1 : TextReader
PORT MAP (
Clk => Clk,
Reset => Reset,
TRout => TRout
);
END struct;