Type declaration in package

[Yiđit Tuncel]

Hello,

I'm trying to design a small project, that is scrolling a text that is entered from keyboard on the 7 segment display of BASYS2 board. I am near the end, but having some compiling issues. I am thinking that the problem arises from a package I declared, that includes the type "array of bytes". The shifter module I wrote uses this type, but there are some errors with it. Basically, cpu does not locate the type I declared in the package.

Here's the shifter module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.mypackage2.all;

entity shifter is
generic ( REGSIZE : integer := 16);
port(clk : in std_logic;
Scan_Dav : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Data_out : out reg_array(REGSIZE-1 downto 0));
end shifter;

architecture bhv of shifter is

signal shift_reg : reg_array(REGSIZE-1 downto 0); --:= (others<='0');
begin
process (clk, Scan_Dav) begin
if rising_edge(clk) then
if Scan_Dav then
shift_reg(REGSIZE-1 downto 1) <= shift_reg(REGSIZE-2 downto 0);
shift_reg(15) <= shift_reg(0);
end if;
end if;
Data_out <= shift_reg;
end process;
end bhv;

Here's the package:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package mypackage2 is

subtype reg is std_logic_vector(7 downto 0); -- a byte
type reg_array is array (0 to 15) of reg; -- array of bytes

end mypackage2;


package body mypackage2 is

end mypackage2;

As I'm new to VHDL, I might have done some basic errors. Also, the package I've written does not show up in the project hierarchy at the lefthand side of the window.

And these are the errors:


ERROR:HDLParsers:524 - "F:/Projeilk/Shifter.vhd" Line 12. reg_array is already a constrained array type.
ERROR:HDLParsers:3010 - "F:/Projeilk/Shifter.vhd" Line 15. Entity shifter does not exist.
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 17. Undefined symbol 'reg_array'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 17. reg_array: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 17. Undefined symbol 'REGSIZE'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 17. REGSIZE: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 19. Undefined symbol 'clk'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 19. clk: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 19. Undefined symbol 'Scan_Dav'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 19. Scan_Dav: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 20. Undefined symbol 'rising_edge'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 20. rising_edge: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 22. Undefined symbol 'shift_reg'.
ERROR:HDLParsers:1209 - "F:/Projeilk/Shifter.vhd" Line 22. shift_reg: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "F:/Projeilk/Shifter.vhd" Line 26. Undefined symbol 'Data_out'.

 

[Thomas Stanka]

On 11 Dez., 20:56, Yiđit Tuncel <tunce...@gmail.com> wrote:
[..]

Data_out : out reg_array(REGSIZE-1 downto 0));
[..]
signal shift_reg : reg_array(REGSIZE-1 downto 0); --:= (others<='0');
begin
process (clk, Scan_Dav) begin

Not an error, but clocked process should contain only clk in
sensitivity list (plus reset, if async reset).

[..]

subtype reg is std_logic_vector(7 downto 0); -- a byte
type reg_array is array (0 to 15) of reg; -- array of bytes

0 to 15 is not identical to 15 downto 0 in VHDL.

your problem is that array size is defined in package, you can't
change that size in a signal declaration
Correct usage would be:

Data_out : out reg_array;
signal shift_reg : reg_array; -- := (others => (others => '0') );

bye Thomas

 

[Andy]

Or:
-- unconstrained array typedef
type reg_array is array (natural range <&gt of reg;

and then:

data_out : out reg_array(regsize - 1 downto 0);
....
signal shift_reg : reg_array(data_out'range);

I usually prefer to use arrays of vectors indexed in the "to" direction. It helps distinguish the array index from the vector index.

Also, I don't think the shift register is going to do what you want, especially if regsize is not 16. Try this:

shift_reg <= shift_reg(regsize - 2 downto 0) & shift_reg(reg_size - 1);

or, to rotate the other way:

shift_reg <= shift_reg(0) & shift_reg(regsize - 1 downto 1);

Andy

 

[rickman]

Let's look at things one at a time...


On 12/11/2012 2:56 PM, Yiğit Tuncel wrote:

Hello,

I'm trying to design a small project, that is scrolling a text that is entered from keyboard on the 7 segment display of BASYS2 board. I am near the end, but having some compiling issues. I am thinking that the problem arises from a package I declared, that includes the type "array of bytes". The shifter module I wrote uses this type, but there are some errors with it. Basically, cpu does not locate the type I declared in the package.

Here's the shifter module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

What the heck!? I'm not yelling at you, but for some reason these
packages were produced a LONG time ago and were a real mess for a
variety of reasons. They were a bad idea at the start and they have
been replaced by numeric_std which is a REAL IEEE standard, not a poser
like the std_logic_arith stuff. Their use has been deprecated for a
long time now and yet the word has not spread to newbies.

I don't know where you learned VHDL, but you should complain to someone
about being advised to use these libraries. Instead use
IEEE.numeric_std.all and learn how to use it properly. It will reward
you well. The main difference is that the poser libraries impose signed
or unsigned types on std_logic_vectors while std_numeric defines new
types, closely related to std_logic_vector, signed and unsigned. You
can use both in the same module with numeric_std but not with the poser
libraries. There are other issues as well.

use work.mypackage2.all;

entity shifter is
generic ( REGSIZE : integer := 16);
port(clk : in std_logic;
Scan_Dav : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Data_out : out reg_array(REGSIZE-1 downto 0));
end shifter;

architecture bhv of shifter is

signal shift_reg : reg_array(REGSIZE-1 downto 0); --:= (others<='0');

Your declaration of the type reg_array includes a range for the index.
You can't override that range in the signal declaration. You can define
the type as unconstrained and then this syntax would be valid. See below.

begin
process (clk, Scan_Dav) begin
if rising_edge(clk) then
if Scan_Dav then
shift_reg(REGSIZE-1 downto 1)<= shift_reg(REGSIZE-2 downto 0);
shift_reg(15)<= shift_reg(0);
end if;
end if;
Data_out<= shift_reg;
end process;
end bhv;

Here's the package:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package mypackage2 is

subtype reg is std_logic_vector(7 downto 0); -- a byte
type reg_array is array (0 to 15) of reg; -- array of bytes

Try this...

type reg_array is array (natural range <&gt of reg; -- array of bytes

end mypackage2;


package body mypackage2 is

end mypackage2;

 

[Rob Gaddi]

On Thu, 13 Dec 2012 13:03:57 -0500
rickman <gnuarm@gmail.com> wrote:

What the heck!? I'm not yelling at you, but for some reason these
packages were produced a LONG time ago and were a real mess for a
variety of reasons. They were a bad idea at the start and they have
been replaced by numeric_std which is a REAL IEEE standard, not a poser
like the std_logic_arith stuff. Their use has been deprecated for a
long time now and yet the word has not spread to newbies.

I don't know where you learned VHDL, but you should complain to someone
about being advised to use these libraries. Instead use
IEEE.numeric_std.all and learn how to use it properly. It will reward
you well. The main difference is that the poser libraries impose signed
or unsigned types on std_logic_vectors while std_numeric defines new
types, closely related to std_logic_vector, signed and unsigned. You
can use both in the same module with numeric_std but not with the poser
libraries. There are other issues as well.

All of the Xilinx and Altera documentation (and for that matter
generated files) still use the std_logic_arith stuff. As a result,
anyone who learns VHDL by studying the examples of the vendor tools
winds up learning to use the deprecated packages.

And in fairness, I can see why they haven't migrated yet. After all,
numeric_std only came into play in VHDL-93. That's practically
yesterday.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[rickman]

On 12/13/2012 1:16 PM, Rob Gaddi wrote:

And in fairness, I can see why they haven't migrated yet. After all,
numeric_std only came into play in VHDL-93. That's practically
yesterday.

I didn't see the smiley...

Rick